Wouldn't it be nice to save 25% to 30%, or even more, in circuit board power dissipation in your next design?
While for some designs such a savings would just be nice to have, for others it's a necessity to make the design competitive using the latest high performance integrated circuits. Why? Because the new ASICs, SoCs and processor technologies can be described in only one way -they are HOT!
What led to this problem? The answer is increasing power density in IC technology. Even with shrinking transistor sizes and lower operational voltages, the number of transistors on a chip, and the frequency at which they switch, has increased at an even greater rate. The result is more power dissipated in a smaller area that ever before.
Converged Network Adapter Evolution
In the converged network adaptor market, integrated ASICs combine the functionality of a network interface card (NIC) with an Ethernet processing core and a host bus adapter (HBA) using Fiber Channel processing cores. Figure 1 traces the development of these highly adapted ASICs from separate functional ICs to devices with multiple core types on a single system on chip (SoC), to the present day Fabric Adapter ASIC capable of handling multiple protocols natively via a single IC core. This feat is accomplished with smaller process nodes and higher transistor counts than ever before possible. Multiple and lower operating voltages, along with higher clock switching speeds, facilitate this processing power in a smaller footprint than
While this advancement is exciting, there are limits to any technology, including these powerful new ASICs. Board designers who use these technology-enabling ICs now have more challenges than ever to deal with. In small, compact board area environments, the design challenges created by higher power densities include:
- High local IC temperatures, which are near or at specified maximums
- The need for heat sinks or use of other heat mitigation measures
- Increased operating temperatures of adjacent devices
Power Management Strategy via Voltage Supply Scaling
Using the example of the converged network adapter card, a new technique for lowering power dissipation is to lower the core operating voltage(s) of the ASIC in question. This is done while making sure manufacturer-specified operating conditions are maintained. The savings can be significant, as the power dissipated is a function primarily of the square of the operating voltage of the device. When load and digital processing conditions permit, the Vcore of the advanced ASIC can be reduced with power savings of 30% or more per IC. Those conditions include I/O loading, clock speed and other parameters such as temperature and operational characteristics.
At appropriate times a circuit designed to control the setting of the Vcore of the ASIC can change the Vout of the supply delivering that voltage. In Figure 2 a dedicated MCU communicates with the ASIC and by implementing a closed-loop trimming algorithm adjusts the Vcore DC-DC converter in real time. The MCU measures Vcore from the DC-DC and then sends digital correction signals to the DC-DC via a voltage generated with an external digital-to-analog converter (DAC).
Challenges of Traditional Voltage Scaling Methods
One of the challenges of implementing a working solution for setting the Vcore power supply to multiple values is the need for multiple external components in a closed loop control configuration. The measurement of the power supply output voltage is subject to the accumulation of errors created by ground potential variations and single-end voltage measurement techniques. Another disadvantage of single-end measurement is that it is not immune to noise. Traditional single end measurement is a poor alternative to differential input sensing and results in accuracies no better than 1.5% error (min). Other MCU-based solution challenges include the need for an external watchdog timer to insure that a hung processor condition does not occur.
Finally, a custom-built solution is the most expensive alternative, especially when a large number of discrete ICs are required. Another item often overlooked is the risk and complexity of the stable closed loop trimming algorithm itself. A hung MCU or over-ranged ADC or DAC condition will result in unpredictable operation. Being too conservative and missing specification values will reduce power savings.
A Complete Power Management Solution
In addition to accurately scaling Vcore for multiple operating values, a complete board management solution should offer all of the following features:
Power Management Integration Benefits
When there is an opportunity to scale supply voltages in applications such as the advanced CNA ASICs, it is important that the programmed voltages be adjusted automatically with speed and precision. To take advantage of lower operation voltages, the adjustment must also be stable over time, temperature and process variations. Using an integrated single chip solution such as the Lattice Platform Manager to set multiple Vcore values insures less than 10mV max error in Vout values over all the conditions noted above. Due to its programmability and simulation capabilities, the Platform Manager device is easy to implement and verify precision operation. Differential sensing is incorporated on these platform management products as a standard feature that makes them immune to errors due to ground voltage difference.
A key benefit derived from setting the DC-DC to a very precise value is that maximum power savings are enjoyed without violating the manufacturer's minimum setting and endangering reliable device operation. In other words, if operation at a lower power setting is allowed, it is important to take advantage of it, since the clock rate will be also be lowered. Any operating voltage higher that the precise minimum allowed would fail to achieve maximum savings while also forfeiting precious performance margins. Precise, closed loop setting of the Vcore supply voltage eliminates this problem and, when set by a precision ADC and reference combination, results in a solution that is stable over operating conditions, including voltage input, temperature and process variations.
Interfacing with a wide variety of DC-DC converters is simplified through the use of design software such as Lattice's PAC-Designer. All required external components (resistors) are computed and determined in advance for optimum control over all DC-DC converter errors. When placed under Platform Manager closed loop control, a power supply's errors are reduced to less than 10mV max error Vout. Designers simply specify what operational voltages they want achieved by various DC-DC outputs and software chooses all the necessary external components and internal device settings to achieve precision trimming of the external power supplies. As various supplies are used again in successive designs, they are captured in a DC-DC component library for reuse, further easing the design task.
A Flexible I2C interface including general purpose I/O (GPIO) that can be programmed to interface directly with proprietary voltage scaling circuitry is now being included in some advanced digital processing engine ASICs and other ICs found in modern circuit board electronics. A device such as the Platform Manager can easily accept these control signals from the advanced ASIC, eliminating the need for an external power supply controller. Instead, this function becomes part of the device's tightly integrated solution.
- Voltage monitoring (all supplies)
- Power supply sequencing
- PCIe requirements for hot swap of 3.3V and 12V
- Power feed control to SFPs
- Reset Tree generation
- I2C link for multiple purpose communications