Home  |  About PSD  |  Community  |  RSS Feeds  |  Subscribe  |  Media Info  |  Join Newsletter  
 
>
>
Tech Talk

 

 

 

IEDM, where the device is king

 PDF

but the material base suggests new approaches to manufacture


Click image to enlarge

Figure 1a: The MoS lattice structure (a) and a schematic of the CVD process for growing single layer MoS, which shows great uniformity and coverage (b).

With a 60-year pedigree the IEDM (IEEE International Electron Devices Meeting) is that pre-eminent forum where the world reports technological breakthrough in the areas of semiconductors, electronic-devices technology, design, manufacturing, physics, and modeling. It is the realized R&D dream, the first steps to producing eventually the electronic components, devices, systems, and applications of the biennial Electronica, now in its 25th year, and alternating with Productronica manufacturing slant. IEDM has also become the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum, phenomenology, optoelectronics, power, energy harvesting, and high-speed devices, not to mention process technology, device modeling, and simulation. This year in December at San Francisco, those who have the thrill of attending will see an increased emphasis on circuit and device interaction. With the ever-increasing transistor count, nanometer design rules, and layout restrictions, circuit-device interaction is becoming highly critical to provide viable technology. This is seen as one new emphasis that includes technology and circuit co-optimization, power to performance to area analyses design for manufacturing and process control, as well as the better known, more traditional CMOS platform technology with its continuous scaling. Among some 220 presentations, which of course includes Intel unveiling its hot trigate manufacturing technology and Europe's Imec presenting a plenary talk, two invited presentations, one tutorial, and nine papers with imec researchers as first authors and co-authored, there are several new material straws revealed for future devices. MoS (molybdenum sulphide) is one of the new entrants cheerfully determined to nudge grapheme slightly off its pedestal. A 2D material, MoS has grapheme characteristics, but unlike grapheme, it also has a wide energy bandgap, which enable fabricators to build transistors and circuits directly from it. MIT researchers will be describing the use of that traditional workhorse CVD (chemical vapor deposition) process to grow the uniform, flexible, single molecular layers of MoS, comprising a layer of Mo atoms sandwiched between two layers of S atoms (figure 1). They then exploited the material's 1.8-eV bandgap to build MoS transistors and simple digital and analog circuits, namely a NAND logic gate and a 1-bit ADC converter. The transistors have demonstrated record MoS mobility > 190 cm2/Vs, an ultra-high on-off current ratio of 108, record current density of ~20 μA/μm, and saturation, as well as putting on the first ever GHz RF performance from MoS. These results would seem to show MoS as suitable for mixed-signal applications, and useful for those that require both high performance and mechanical flexibility (reference 1). PCM (phase change memory) has frequently been a star performer at IEDM over the last handful of years. For 2012 however a neuromorphic, or brain-like, electronic system that mimics cognitive functions is the current showpiece and focus of research through its potential for complex tasks such as pattern-recognition. IEDM papers in 2011 described studies using programmable PCM synapses in neuromorphic systems to carry out a function STDP (spike-timing-dependent plasticity). STDP is an electronic analog of a brain mechanism for learning and memory. An electronic system that accurately performs STDP can be said to be learning. This year, a team led by Korea's Gwangju Institute of Science and Technology details a high-speed pattern recognition system; comprising CMOS neurons and an array of RRAM (resistive-RAM) based synapses, which also demonstrate STDP (reference 2).

The 1-Kb RRAM array has a simple cross-point structure and may be scalable to 4F—the theoretical minimum size for a cross-point array. The work shows the feasibility of using neuromorphic architecture for high-speed pattern recognition and charts the work in a comparison of artificial-brain projects (table 1). Without memory, much of the electronics business would be missing, but flash memory lifetimes are currently limited in use, because repeated P-E (program-erase) cycles degrade the tunnel oxide, which insulates the flash memory cells. In principle, while heating the oxide repairs the damage, this thermal annealing has been impractical, as flash memories do not tolerate high temperatures and long baking times. Now it appears that Macronix researchers have managed to build flash memories that could self-heal, by using tiny on-board heaters that provide thermal annealing, just at the spots where it is needed.

They have modified the wordline from a single-ended to a double-ended structure, which in turn enables current to be passed through the gate to generate Joule heating (figure 2). High temperatures, > 800 °C, accordingly were generated, but only in the immediate proximity to the gate. The devices demonstrated record-setting endurance of > 100 million P-E cycles and with excellent data retention. Interestingly, is thought to be temperature-independent (reference 3). That other electronics Holy Grail, the quest for flexible circuitry with its promise innovative biomedical, security, wearable, and other uses to date finds plastic substrates not compatible with the high temperatures and harsh processes needed for high-performance CMOS devices. It now that looks to be in IBM's remit, as researchers have developed logic on plastic with high performance CMOS circuits, including SRAM memory and ring oscillators, on a flexible plastic substrate. Known as ETSOI (extremely thin silicon-on-insulator) devices, these have a thickness of just 60 angstroms. IBM built them on silicon, then used a simple, low-cost room-temperature process called controlled spalling, which essentially flakes off the Si substrate (reference 4). Engineers then transferred them onto flexible plastic tape. The devices had gate lengths of < 30 nm and gate pitch of 100 nm. Ring oscillators had a stage delay of just 16 ps at 0.9 V, and this is believed to be the best-reported performance for a flexible circuit.

A slight degradation of delay for the flexible sample, after the layer transfer, comes from degradation of p-FET performance due to strain effects. The final 100-mm-diameter flexible ETSOI circuit is on plastic (figure 3). The unreleased MEMS (micro-electro-mechanical systems) resonator, another M.I.T. device, might in passing seem to be just a curiosity, but it looks to be very helpful player in the communications and timing sectors. A common task in circuit design is to generate reference frequencies for timing and communications purposes, and one way to do this is via vibrating micromechanical resonators. A challenge with MEMS technology is integration of these MEMS devices with CMOS circuitry. An aspect of the problem is the difficulty of successfully releasing, or removing the MEMS devices from a substrate after fabrication, so that they can be integrated with CMOS.

Now an M.I.T team avoid that need altogether, by driving the MEMS resonator electrostatically, using deep trenches, that function as capacitors (figure 4). The resonator frequency could then be tailored easily, via the lithography used to build the trenches, and the trenches also serve as acoustic Bragg reflectors to confine and localize the resonance vibrations. Built using a 32-nm SOI process, the 3.3-GHz MEMS resonator had a Q of 2057—the highest reported to date for an unreleased MEMS resonator. The work paves the way for high-Q, multi-frequency sources to be built and intimately integrated in CMOS with no need for additional processing or packaging (reference 5).

References: 1. Paper 4.6: Wang, H., et al, Large-Scale 2D Electronics Based on Single-Layer MoS2 Grown by Chemical Vapor Deposition, Massachusetts Institute of Technology 2. Paper 10.2: Park, S., et al, RRAM-Based Synapse for Neuromorphic System with Pattern-Recognition Function, Gwangju Institute of Science and Technology 3. Paper 9.1: Lue, H.T., et al, Radically Extending The Cycling Endurance of Flash Memory (to >100M Cycles) by Using Built-In Thermal Annealing to Self-Heal the Stress-Induced Damage, Macronix International 4. Paper 5.1: Shahrjerdi, D., et al, Advanced Flexible CMOS Integrated Circuits on Plastic Enabled by Controlled Spalling Technology, IBM 5. Paper 15.1: Wang, W., et al, Deep Trench Capacitor Drive of a 3.3-GHz Unreleased Si MEMS Resonator, Massachusetts Institute of Technology Power Systems Design

 

 

 

  Home  |  Site Map  |  Contact  |  Privacy Policy  |  Terms of Service  |  Copyright © 2014 POWER SYSTEMS DESIGN, All rights reserved