Dedicated power management ICs boost performance

The netbook PC has evolved significantly since its relatively recent inception. What started off just two years ago as a small PC intended primarily for the ‘One Laptop per Child’ project with limited capabilities is now emerging as an important and popular business tool. Effective power management techniques can further improve efficiency and shrink the required board space in the new generation of ultra-portable lightweight computers.

By Michael Maurer, Technical Marketing Manager, Dialog Semiconductor

Crucially, the small size, low weight and, more recently, integrated 3G-connectivity of netbooks make these devices an ideal way to maintain contact with the office via the internet when travelling. As a result, netbooks and similar small format portable computing devices need to deliver the functionality of larger business PCs. In particular, they must keep users in touch, entertained, and productive while on the move.

However, delivering this means silicon architects are posed with substantial challenges. Designers must find ways of supplying sufficient computing power to run sophisticated operating systems and application software from battery power sources whilst delivering a rewarding user experience with acceptable run times even when devices are connected to 3G mobile broadband for several hours at a time.

And, as the netbook market becomes more and more crowded it is becoming increasingly difficult to deliver differentiated products. But, accurate power management and a shift from discrete solutions will allow designers to take the next step.

A quick history of the portable PC processor

Traditionally, the architecture of choice for devices that wished to exploit the massive base of Windows or Linux software was the IA-32 instruction set that Intel introduced for its first 32-bit processor in 1986. This is now changing and a growing number of chips are being created to meet the processing needs of the standard netbooks, the ultra-portable sub-netbooks and the plethora of devices in between. These demonstrate several new approaches to portable computing and provide designers with a hardware platform that’s architecturally similar to previous PCs at instruction-set level, but with order-of-magnitude reductions in power consumption and circuit-board real estate. As a result, it’s now possible to construct pocket-sized mobile internet devices (MIDs) that run familiar applications and embody additional functionality such as GPS mapping.



Qualcomm recently demonstrated an ASUS Eee PC that used its Snapdragon processor. This features integrated 3G broadband and GPS connectivity and Google's Android operating system was used for the demonstration. The Snapdragon is a relative newcomer to the market. However, the leading family of such chips in systems sold today is still Intel’s Atom processor. It was used in the original Asus Eee and is now in similar devices from numerous manufacturers including Acer, Fujitsu, HP and Samsung. For this reason, the following technical data discusses power management with respect to the Intel Atom Z5xx. The following principles can also be applied to similar processors.

Power down by 90%, area by 80%
The Atom Z5xx series uses a 45nm CMOS process technology to fabricate around 47 million transistors on 25mm2 of silicon. Designers are provided with seven options that span 800MHz to 2GHz operation with 400 or 533MHz front-bus interfaces. Two thermally-enhanced packages are also available to handle nominal power dissipation levels that range from 0.65W to 2.64W.

However, it’s the IC’s power efficiency that’s arguably the greatest achievement of both the Atom and Snapdragon designs.
Power management hardware can take this further and, if precisely controlled, a top-speed netbook processor will consume just 2.5W. Compared with the 35W that the mobile Core 2 Duo processors typically consume, this is a power saving of more than 90 percent.

Another major achievement is the reduction in circuit-board area that this new generation of processors enable. Looking once more at the Atom; the processor is intended to work alongside a system controller hub (SCH) chip that integrates memory and I/O controllers together with Intel’s Graphics Media Accelerator 500. It is estimated that using the Atom shrinks circuit-board area from 3,592mm2 to just 666mm2, a saving of more than 80 per cent. And, to build a complete system, you only need add your choice of peripherals, a flash memory to hold EFI (extensible firmware interface) BIOS code, some DDR2 RAM, a clock source that meets the clock synthesiser specifications and power management hardware to manage the platform’s multiple power domains and control supply sequencing.

However, these latter requirements are not trivial.

A tailored solution
The first companion PMIC for the Intel Atom, the DA6001, was announced earlier this year. Here we look at the development of the DA6001 with respect to the Atom and determine the key steps required in the development of a tailored power management solution.

 Precisely tailored PMICs simplify power management in portable devices

The Atom’s low power states operate at two levels. At thread level, on-chip logic implements what loosely equates to ACPI (advanced configuration and power interface) protocols for processor power states. Because a change in the core’s power configuration only occurs when both threads request it one thread can sleep while the other operates normally. Two software interfaces are available to control these features. The first mechanism exploits extensions to the processor’s MWAIT instructions while the second consists of reads to the chip’s ACPI registers in I/O space that the processor internally maps into a set of equivalent MWAIT codes. This second mechanism does not directly result in any I/O accesses on the front-side bus.

By contrast, a package level change requires external intervention. Again, the results generally map to processor states from C0 (active execution) through the C1 (one thread halted) and C2 states (one or both threads halted but still performing bus snoops to maintain cache coherency) to the C4, C5, and C6 sleep modes. These sleep modes have multiple layers that lower the processor core power supply to its minimum value. In the C6 mode an on-chip SRAM powered from the I/O supply holds the processor’s state until a break event triggers a sequence that returns the processor to normal operation.

The system controller hub IC also has several sleep modes and therefore state transitions and handshake terminations to be controlled with supply domains that require switching off/on. The S3 ‘suspend to RAM’ state writes the current state of the machine and the operating system to DDR2 RAM that is automatically refreshed by the memory controller. Most system components are powered down in this state, leaving a suspend power domain active to allow the GPIO, PCI Express, and USB interfaces to wake up the system. The S4 state is a hibernate or ‘suspend to disk’ state, which saves the machine and operating system states to disk, enabling the system to be essentially powered down. The very similar ‘soft-off’ S5 state does not save the operating system’s context.

Software can configure the processor to run at different frequencies and voltages to yield the greatest efficiency in a given scenario. Changing frequency requires the reprogramming of the processor’s PLL (phase-locked-loop), whereupon the processor automatically adjusts the core voltage to a suitable level and the PLL locks in. Furthermore, an enhancement to the thermal monitor mode can automatically cause the processor to move to a lower-voltage and lower-frequency mode if the die temperature becomes too high. This feature is configurable in software by setting appropriate values within the processor’s MSR (model-specific register).

The processor changes core voltage by writing new values to its seven VID (voltage identification) pins to request VCC levels from 0.3V to 1.2V in 12.5mV increments. To ensure glitch-free transitions, the processor ramps the voltage that an IMVP (Intel mobile voltage positioning) compliant regulator supplies. Actual maximum and minimum VCC voltages for high and low frequency operation differ slightly between Atom variants, with most operating between 0.75V and 1.10V at maximum currents of 2 to 4A. The 0.3V core-voltage level applies during the C6 sleep state and must not fall below this value.

The VCCP plane that powers the processor’s I/O tracks the main core voltage. Optionally, you can create a split VTT plane that makes it possible to disconnect power during C6 from all I/O pins except those that are necessary to wake the processor. This is accomplished by the system controller hub asserting a signal which gates an external MOSFET; this process reduces leakage currents by about 30 per cent. And during all power states the companion VCCP6 plane must be held at 1.05V.
The front-side bus employs a hybrid CMOS/GTL (Gunning transistor logic) interface to minimise power dissipation for most signals while maximising signal integrity for strobe lines, this requires the motherboard to supply reference voltages for the respective transceivers. In addition, the PLL requires a clean 1.50V supply that’s permanently present.

More circuits, more power supplies

Other platform elements complicate the power supply and management requirements. For instance, the Intel system controller hub, SCH US15W, uses the same core and front side bus voltages for its host processor interface, but requires additional supplies for its DDR2 memory controller, graphics display system and numerous I/O interfaces. These additional levels include 1.5V, 1.8V, 3.3V, and 5V, several of which are dedicated to functions such as the display PLL, the LVDS (low-voltage differential signalling) interface, the PCI Express interface, and the USB system. And of course, the DDR2 and EFI memories require power sources and control that closely couples with the processor and its system controller hub.

Powering multiple power planes with quite different current requirements in consumer-volume devices demands a holistic approach that takes maximum advantage of the available silicon area at the lowest possible cost. For instance, existing power-management ICs (PMICs) that target the ARM-dominated world of baseband processors and RF-interface platforms that lie within virtually every mobile phone, boast a complement of fully-integrated switch-mode and linear regulators. And, in the case of a high-end smart phone, these can individually control as many as 30 circuit blocks.

However, the relatively high current levels that the core, system controller hub and memory systems require make it more cost-effective, and reasonable in terms of chip power dissipation, to partition supplies into those that can be fully integrated and those that better suit driving external MOSFETs. Using external MOSFETs also frees the designer to specify more efficient devices as they become available – changes in MOSFET design methods, which now focus on switching speed rather than resistance levels, reinforce the need to take this external component approach.

Dedicated PMICs improve efficiency and shrink board size
When precisely configuring the power management requirements of processors such as the Atom or Snapdragon, a long list of essential and desirable attributes should be considered. Essential requirements include a full complement of power supplies to efficiently down-convert input voltages to levels that suit the Atom platform’s multiple power planes. Similarly, some form of supervision and control is essential to handle the system’s start-up and shut-down sequences without any external intervention.

To provide a minimal footprint solution a dedicated PMIC is essential. This will include all the hardware and software ‘hooks’ necessary to seamlessly connect with the Atom, system controller hub and DDR2 / EFI memories.

A cutting-edge discrete power management solution will require at least 200 active and passive components  

Dedicated companion PMICs come with several benefits, most notably lowering the number of external components, thereby shrinking the required board space. By comparison, a discrete-component approach to satisfying all of the Atom platform’s requirements can consume as many as 20 active and 180 passive components. The discrete approach also requires a microcontroller that runs all of the time to monitor and control transitions between the processor’s operating modes. A state machine within the PMIC that replaces a conventional microcontroller can reduce this function’s power consumption from several mA to around 100uA, and renders the need for programming obsolete.

Looking once more at the Atom, to provide a universal solution for all Atom Z5xx-series parts, the PMIC must integrate an IMVP-6 compliant switch-mode regulator that provides up to 4A of core power. A synchronous buck-converter that drives a pair of external MOSFETs suits downconverting input voltages of 3.6 – 5.25V to the levels that the Atom’s VID pins dictate with minimal power loss. The voltage control loop should achieve around ?1.5 per cent accuracy, and including a pulse-skipping mode can greatly contribute towards conserving power under light load conditions. Using a switching frequency of 1MHz allows the use of inductors as small as 1.5uH.

5.2A is required by the system controller hub and its front bus interface while another 3.2A is necessary to power the memory system that supports up to 2GB of DDR2 RAM. Two similar integrated buck converters - that again drive external MOSFET pairs - optimally suit these power domains and require voltage accuracies of around ?3 per cent. Sensing the output voltage at the point-of-delivery maintains best tolerance, while using 1MHz-level switching frequencies constrains filter component footprint. Allowing for a maximum of 1100mA, the lower current needs of the platform’s hardware engines make it possible to fully integrate a further buck converter that runs on a fourth phase of the internal frequency of 2MHz. It’s desirable to drive all of these buck converters from a spread-spectrum clock source, with a spread of about ?45 kHz being sufficient to minimise EMI concerns.

The six remaining power domains have current demands that are low enough to permit low-noise, low-dropout-voltage linear regulators that are easy to integrate. Proprietary techniques can reduce their quiescent power consumption to a point where separate low-power modes are unnecessary. Ideally, an additional dedicated regulator should be included to sink and source current, driving the DDR2 RAM’s termination resistors and maintaining their mid-point reference voltage.

The PMIC should also satisfy the Atom platform’s clock-source needs, which must comply with Intel’s CK610 specification. Three fractional-division PLLs with spread-spectrum capability that operate from a 14.31818MHz crystal reference provide a good solution to this. The inclusion of a charge pump will maintain the 5V domain, even if the input supply falls below this level. And, adding a two-channel, 10-bit analog-to-digital converter, which is capable of running autonomously, eases the monitoring of voltages and temperatures, to ensuring the system remains within its design parameters.

Conclusion
This new generation of processors significantly helps designers to meet the growing demand for truly portable PCs without compromising on functionality or battery life.  
Competition in the market has led to a plethora of devices that sit between the standard netbook and ultra-portable sub-netbook. This does, however, make it increasingly difficult for manufacturers to offer differentiated products.

Through precisely tailored power management solutions designers will be able to make the next leaps forward in terms of battery life.

This improved efficiency means lighter, smaller form factor devices can be created with fewer components, that run more complex operating systems, and can remain connected via Wi-Fi, Bluetooth, GPS and 3G mobile broadband for many hours without needing to recharge.

Two years ago netbooks may have been intended as simplistic, inexpensive PCs but advances in processing technology, technology integration and power management have ensured they’re now the ultimate portable business machines.

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