Modern portable electronics rely on extracting every last Coulomb of charge from the batteries they contain.  The trend in the past has been to improve both the size and efficiency of power supplies through technology such as trans-mode conversion. Looking forward to 2010 and beyond, attempting to extract a few additional percent of conversion efficiency from power supplies will take a back seat to new, more efficient methods of using energy to accomplish the same function.  Here we examine trends in system architecture and integration of power systems that go well beyond what would be possible for power supplies alone.

By Richard F Zarr, PowerWise® Technologist, National Semiconductor

Since the beginning of the 21^st century, there has been a convergence of function and a drive to make things mobile.  The Apple iPhone is a classic example of fusion – the combination of cellular communications, entertainment and Internet access. This trend has driven both mobile processing power as well as energy management to provide the best, long lasting user experience possible with today’s limited battery technology.  However, the power supply is only part of the equation. Providing 94% conversion efficiency is good, but redesigning the system to use 30% less energy is far better.

Where to begin

Most designers begin their new designs based on what was done previously.  This is often the case due to time constraints or lack of personnel.  What’s interesting about this tactic is that inefficient subsystems can continue to propagate into newer designs.  It is not always easy, but gains can be found by re-evaluating these subsystems and how they perform their function.  Since power subsystems have been the focus for many years, their efficiencies have greatly improved.  Most off-the-shelf integrated switching regulator designs can easily top 90% power conversion efficiency.

Going forward, these gains will not be so easy.  Now only single-digit efficiency gains in the power supply can be found, so designers must look elsewhere for improvements.  It is not always obvious, but rethinking how a system solves a problem can yield results.  For instance, finding a better algorithm to encode or decode a data stream can result in a lower frequency clock thus saving power. Sometimes, digital is not always better than analog.  Sometimes using analog processing to supplement or replace digital processing can also greatly reduce power. 

Figure 1 shows two block diagrams of a wireless industrial vibration monitor – one using conventional DSP processing and the other using energy harvesting to power an all-analog envelope (excessive vibration at various frequencies) detector.  The traditional way is to convert everything immediately to the digital domain and process the information with DSP functions.  This consumes a great deal of power since the ADC and DSP must be active during the sampling and calculations.  The analog assisted version uses a continuous-time micro-power filter to monitor for various frequencies along with their amplitudes.  Once a limit is reached, a wake-up call is sent to the microcontroller to signal the monitoring station.  Only during that time is the battery in use.  The mechanical energy harvested from normal vibrations power’s the analog front end.  The microcontroller can even wake up periodically to report normal status to ensure normal operation and still use a much smaller battery.

The trend will be to provide more monitoring capabilities along with wireless communication for ease of deployment as well as placing sensor where no convenient power exists.  This is especially important in applications such as home land security where monitoring must be placed in remote areas.  The cost of the equipment will be secondary to the cost of replacing batteries or the liability of system failure due to dead cells.  

Going deeper

 Beyond the overall equipment design are the system-on-a-chip implementations.  Many are now designed in 65nm or smaller geometry CMOS processes. The trend has continued for quite some time to place more transistors on a single device to provide more functionality in a smaller space.  The problem is that more transistors switching faster increases energy consumption.  Equation 1 shows the fundamental relationship between the energy consumed in CMOS and the supply voltage, clock frequency, internal capacitive loading and leakage terms as well as how long a task is running.  Looking at the equation there are two major terms – the dynamic component and the static component.  The dynamic term suffers the most from supply voltage due to the squaring of the voltage term however leakage is becoming a more serious problem at smaller geometries.  This is primarily due to the scaling of the transistors.     

Equation 1: Fundamental CMOS energy consumption

As the transistors shrink, the oxide thickness needs to also shrink in thickness. This causes electrons to leak through the oxide by tunneling or finding paths via the drain and source extensions. The transistors also suffer from the sub-threshold leakage where the transistors are conducting even though the gates are below the turn-on threshold.  Some of this is due to short channel effects such as Drain Induced Barrier Lowering which moves the threshold and increases leakage.

Many process techniques are being used to control static losses such as the introduction of Hafnium based oxides which electrically have the correct dielectric constant for the scale, but are mechanically thicker to prevent tunneling.  However, architectural changes can help solve both the dynamic and static loss issues.  The obvious first step would be to allow a system to dynamically alter the supply voltage when the frequency is reduced – this is known as Dynamic Voltage Scaling and has been used for years especially in microprocessors for mobile applications.  When the loading on the processor is reduced, a command is sent to the power management unit (PMU) which can reduce the voltage saving significant energy.  This technique can only compensate for the frequency of operation, but does nothing to adapt for the variations in process or the operating conditions such as ambient temperature.

Figure 2: Adaptive Voltage Scaling (AVS)

An improved technology pioneered by National Semiconductor in early 2000 is called PowerWise® Adaptive Voltage Scaling (AVS).  This technique compensates for the frequency of operation and additionally compensates for process or temperature variations including aging.  Figure 2 shows the basic block diagram of how a system using AVS works.  The HPM or Hardware Performance Monitors are synthesized along with the application and continuously monitor the performance of the process.  The status is reported to the Advanced Power Controller (APC) which determines if the process is running fast enough for the application.  If the process needs to go faster, the APC sends a command to the external Energy Management Unit to increase the supply voltage in very fine steps until the performance level is met.  Conversely, if the process is running faster the same function reduces the supply voltage. This can dramatically reduce the energy consumption of the device since the majority of the time the process is faster than it needs to be and the ambient temperature is not at the extremes.  ASICs using this technology have seen savings up to 40% and more in specific applications.  These gains are far greater than trying to improve the power supply efficiency a few percent.

Conclusion

Power supplies have matured and now routinely provide conversion efficiencies of over 90%.  Engineers need to look beyond the power supply for savings and rethinking old methods of building functional blocks. Additionally, re-architecting existing designs can yield significant energy savings as well.  With trends moving to more remote wireless applications and more processing with less power, new techniques must be employed to reduce energy consumption and meet the demand of the next decade.

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