Improve efficiency with variable output voltage

The need to minimize power loss drives engineers to incrementally improve efficiency in multi-stage power supply designs for the 100-120V line power used in North America, Japan and Taiwan, and the 220-230V AC mains used in Europe and in the rest of the world, with variable PFC output. Careful consideration of the PFC stage design helps maximize efficiency for the overall power supply

By Aung Thet Tu, Product Line Director, Power Conversion America, Fairchild Semiconductor

A typical offline or ac-dc power supply includes a number of stages. Generally a bridge diode rectifier creates an unregulated dc voltage from the ac input. The downstream dc-dc converter stages deliver the regulated stable dc output voltages required for the application at hand. The PFC stage sits between the rectifier and the dc-dc converter stage (Figure 1 depicts a typical rectifier and PFC stage). The PFC stage leverages switch-mode technology so that the PFC converter draws nearly sinusoidal AC current that is in phase with the line voltage and therefore yields a PF (real power / apparent power) close to the ideal value of 1.   

Figure 1: A typical PFC power stage

Theoretically, you could use most any switching converter topology in the PFC stage. The boost topology is a popular choice for several reasons. The boost converter has a relatively small BOM (bill of materials) when line filter requirements are considered. Moreover, typical boost converter designs minimize EMI noise.

Let’s consider a typical universal PFC boost converter. With a 220V input, the output of a full bridge rectifier is in the range of 350V to 360V. The boost converter design must output a higher voltage than the input to both ensure proper boost operation and to shape the input current waveform. Subsequently, typical PFC boost converters have an output voltage in the range of 400V.

Why PFC output voltage matters

Generally, a higher voltage delivers more efficiency in terms of the energy stored in the PFC stage. Conversely, a higher output voltage equates with greater switching losses here – especially in light-load conditions. A lower output voltage from the PFC stage can incrementally increase total system efficiency. It can improve the PFC stage efficiency at light load condition by reducing capacitive switching loss. It can also improve the efficiency at low line voltage by reducing the voltage conversion ratio because a large voltage conversion ratio (Vo/Vin) results in severe conduction loss in the boost switch. The flip side for the downstream dc-dc converter is that it has to be designed for a wide input voltage range which is not good for efficiency.

DC-DC converter ramifications

While the ability to adjust PFC output voltage might be valuable in absolutely maximizing efficiency, we need to consider how a variable PFC output might affect the dc-dc stage. And then we need to discuss practical ways to handle the adjustment realizing that the adjustment scheme and the dc-dc-stage design are very much intertwined.

Hold-up time is one power-supply spec that comes into play. Hold-up time specifies how long the supply will continue to output a voltage above a specified minimum after the AC input goes away. The input voltage range of the dc-dc converter affects hold-up time as does the output capacitor that stores energy at the output of the PFC stage. Power-supply designers must ensure that a lowered PFC output voltage does not cause the dc-dc stage to fail the hold-up time requirement. At the same time, the dc-dc stage must be designed based on the range of the variable PFC output.

Designers must consider two dependent variables when contemplating an adjustable PFC output voltage. In an input-voltage-dependent design, sometimes referred to as the boost follower technique, the PFC output voltage is set proportionally to the rms value of the ac input. Typically, a predetermined constant offset value added to the AC input determines the PFC output.

Alternatively, the output power of the PFC stage can serve as a reference for PFC voltage adjustments. While the algorithm is slightly more complex than a linear function, essentially PFC output voltage can be controlled as a linear function of output power. You do have to ensure that PFC output voltage never drops below the input voltage in such a scheme. Under high-line voltage, low-load conditions, the linear control could result in such an undesirable circumstance. So a typical implementation must also monitor the input voltage and use that information to gate the floor of the PFC output range.

Moreover, a PFC stage operating at reduced output during light load conditions would not respond as quickly to a rapid load increase as would the dc-dc stage. So the designer must carefully select a floor for PFC output voltage to correspond with the minimum input of the dc-dc stage.

One of the ramifications of universal the input voltage dependent design is a typically broader range of PFC voltage output. Therefore, the designer must develop a dc-dc stage that can handle that input range. The wide output voltage range also hampers compliance with hold-up time specifications and typically would require a large output capacitor value.

A PFC converter that uses output power as a reference is called a load-dependent design. The PFC output voltage range is relatively narrower, resulting in a simpler dc-dc converter design and a relatively smaller output capacitor.

 A simple load-dependent implementation  

It turns out that the load-dependent scheme is also relatively simple to implement. Instead of a continuously variable PFC output capability, designers can turn to an implementation where the PFC voltage output is adjustable between fixed levels. For instance at full load and full line power, the PFC will be nominally 380V. At some trigger point of lighter load and/or lower input voltage, the output might drop to 350V. The graph in Figure 2 depicts such an operational scenario based on load. When the load drops to approximately 35%, the PFC output drops. When it climbs beyond 50%, the output returns to the nominal level.

Figure 2: Simple PFC output adjustment scheme

Design teams can implement this simple adjustable output PFC converter suitable for most consumer electronic applications. The Fairchild FAN6982 Continuous Current Mode (CCM) PFC Controller, for instance, integrates a “range” function that can modulate the PFC output. This feature on the FAN6982 can be enabled by simply pulling the EN (Enable) pin high. To disable the range feature it can be pulled low to signal ground (Figure 3).

The designer still has some flexibility in setting of the lower PFC output voltage. When low-load and low-line conditions trigger a transition to the lower PFC output level, the converter instigates the action by enabling a 20µA internal current source that is internally connected to the inverting input of the error amplifier which is the voltage feedback input (FBPFC pin). By changing the apparent feedback divider ratio, the error amplifier adjusts to provide a lower PFC output voltage. You can set the voltage of the lower PFC output level by adjusting the bottom resistor (R_FB2) of the two-resistor voltage divider between the output voltage and ground (Figure 3).

Figure 3: PFC output voltage adjust configuration on FAN6982

Other keys to maximum features and minimum external component counts

Let’s focus for the moment on the protection area. A failure in a PFC feedback circuit could prove catastrophic to a power supply with the PFC output exceeding operating limits. In the case of the FAN6982, an internal protection circuit monitors the FBPFC pin. The circuit can detect open-, short-, and floating-circuit faults in the voltage feedback path. Fairchild calls the capability TriFault Detect™. The capability requires no external components and complies with the UL 1950 safety standard.

Brownout is another significant concern. Your design should ensure that the PFC stage does not enter an over-current state with sagging input voltage. The FAN6982 internally monitors the VRMS pin. When the voltage drops below the 1.05V threshold, the IC shuts down the PFC stage. The boost stage is enabled once VRMS reaches 1.9V.

One feature that many applications require these days is soft start. The design must limit the input current during startup to prevent saturation of the boost inductor and over-current stress of the switching device. You can avoid that situation with a soft-start design that sequences power to the stages.

In a PFC-based implementation, the designer needs to address soft start in both the PFC and dc-dc stages. The FAN6982 includes an integrated PFC soft-start function. The controller monitors the PFC output voltage and clamps the output of the voltage error amplifier when the voltage drops below 96% of a nominal value. In that mode, the output of the error amplifier (V_EA) is clamped, the current loop limits the line current, and the PFC exhibits a lengthened rise time until the PFC output voltage passes through the threshold and the voltage error amplifier again assumes normal operation (Figure 4).    

Figure 4: PFC soft-start implementation

One final area of interest is input current shaping because that function contributes heavily to optimizing the power factor. The FAN6982 integrates current shaping capability using a gain modulator. The AC input current, voltage error amplifier and VRMS signals drive the modulator. The output automatically adjusts the reference input to the current-control error amplifier.

Summary

Careful consideration of the PFC stage design can result in maximum efficiency for the overall power supply in popular applications such as PCs, servers, industrial power supplies and consumer electronics such as display power. A simple adjustment of PFC output voltage design incrementally improves the efficiency. A highly integrated PFC controller can realize such energy savings and provide circuit protection and features such as soft-start capability with a minimal external component count.

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