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New controller addresses energy saving in server power system New government and industry standards and regulations require increased efficiency across the whole load range for data and telecommunications server power systems. One example is the “ENERGY STAR® Program Requirements for Computer Servers,” effective May 15, 2009. As a result, different aspects of designing a power supply including system architecture, topology, components and control must be considered together. This article focuses on efficiency improving control and a concept controller for the DC/DC converter. By Rais Miftakhutdinov, Power Supply Control Technologist, and Zhenyu Yu, Marketing Manager, Texas Instruments Striving for efficiency aa High efficiency at full load has always been critical for data and telecommunications server power supplies. Recently, however, the focus has shifted to efficiency over the entire load range. This is because these systems spend significant time operating at mid- and light-load. New standards and regulations have been introduced to address this shift. One example is the ENERGY STAR Program Requirements for Computer Servers, Version 1, effective May 15, 2009. This regulation sets efficiency and power consumption requirements for server power supplies as in Table 1. aa
aa Table 1: Efficiency requirements for single output AC/DC or DC/DC server power supplies.
Typically, a server power supply includes a power factor correction (PFC) stage followed by an isolated DC/DC and low-power standby power supply. The efficiency goal for each part of the power supply must satisfy the ENERGY STAR requirements. This is illustrated in Table 2 for a server power supply that includes PFC, 660-W DC/DC and 5V/2A standby.
jkj Table 2: Efficiency goals for PFC, standby power supply, and 660-W DC/DC converter.
Power saving control strategies The next step for designing a DC/DC converter is to select the optimal topology and control including: · Interleave phases for better current and temperature distribution at maximum load with phase-shedding at light load; · Synchronous rectification using MOSFETs with diode emulation at light load to avoid current circulation. It is best to shut off rectifier MOSFET drive circuits at light load. Performance of the synchronous rectifier depends significantly on accurate timing between primary and secondary side switches; · Proper implementation of zero-voltage-switching (ZVS) and zero-current-switching (ZCS) reduces switching losses. This requires optimal adaptive or predictable delays between switching events; · Optimally adjusting the intermediate bus voltage, drive voltage and other system parameters; · Smooth transition from one mode to another, depending on operating conditions. For example, from continuous current mode to discontinuous, from fixed frequency to frequency foldback, etc.; · Proper use of pulse skipping or burst mode at light and no load. It is preferable to use ZVS topologies for post-PFC converter, like phase-shifted full-bridge, asymmetrical half-bridge and LLC resonant. Phase-shifted full-bridge has a long history of usage due to the combination of useful properties. But, to maintain high efficiency over a wide-load range, additional optimization in control is needed. Phase-shifted DC/DC with advanced controller Major advantages of a phase-shifted converter are ZVS of the primary side MOSFETs, fixed frequency PWM, reliable handling of shorts with cycle-by-cycle current limiting, and wide input voltage range. A major drawback is current circulating through primary switches during off interval and the need for snubber or clamping circuits for the synchronous rectifier. Efficiency improvement is achieved by using synchronous rectification, control that provides ZVS over the entire load range, accurate adaptive timing between primary and secondary MOSFETs, and special operating modes at light load. There are a number of digital and analog controllers from Texas Instruments to address this application. A simplified diagram of such a converter with a conceptual controller is shown in Figure 1.
Figure 1: Phase-shifted, full-bridge converter with advanced controller The controller is on the secondary side, allowing easier communication and better handling of certain transient conditions that require fast direct control of the rectifier MOSFETs. For 12-V output, using a center-tapped rectifier is a popular choice.
To maintain high efficiency across the load, the converter operates in normal synchronous rectification mode at mid- and high-load, transitions to diode rectifier mode at light load, and to burst mode as load drops further (Figure 2). All these transitions are based on primary side current sensing using current transformer (CT). Proper timing between primary and rectifier MOSFETs is critical for highest efficiency and reliable operation. The controller adjusts the turn OFF timing of rectifier MOSFETs as a function-of-load to ensure minimum body diode conduction time and recovery losses.
To ensure ZVS conditions over the entire load range, the controller adjusts delay time between primary MOSFETs in the same leg in accordance to load. The controller also limits the minimum ON-time of pulse at light load, allowing the storage of sufficient energy for ZVS. It is necessary to prevent reverse current flow through rectifier MOSFETs and output inductor at light load during parallel operation and under certain transient conditions. Such reverse current results in the circulation of extra energy between source input and load and, therefore, causes increased losses. Another negative effect is the loss of ZVS. The suggested control scheme prevents reverse current flow while keeping most of the benefits of synchronous rectification. At a pre-determined load current, the controller reduces synchronous rectifier drive signals from overlapping to 50 percent, and then gradually reduces their pulse duration until shutting off at the second predetermined threshold. This is called transition mode.
Figure 2: Timing diagrams and transitions between power saving modes
Below a certain current threshold, the rectifier-MOSFET-drive related losses exceed the savings provided by synchronous rectification. This is when it is beneficial to disable the drive circuit and use body diodes or external diodes in parallel with the MOSFETs for output rectification. This mode of operation is called discontinuous-current diode-rectification mode. At very light and no load, the duty cycle, demanded by closed-feedback-loop control, can be very low and could lead to loss of ZVS and increased switching losses. To avoid this, the control circuit limits the minimum ON-time pulse applied to the power transformer. Therefore, the only way to maintain regulation under this condition is to skip pulses. The controller skips pulses in a controllable manner to avoid saturation of the power transformer. This is called burst mode.
The block diagram of this controller is shown in Figure 3. This controller provides adaptive timing between primary and secondary MOSFETs, and adaptive delay for primary switches in the same leg based on the current sense signal (CS). At light-load the efficiency management block provides optimal transition between different modes in Figure 2 as a function of the CS. Additionally, the controller provides all major functions and features usually found in such ICs.
Figure 3: Block diagram of the advanced phase-shifted contoller IC Conclusion The new industry requirements and regulations for increased efficiency over a wide-load range for server power supplies have been outlined and control strategies providing high efficiency over entire load range listed and discussed. The phase-shifted full-bridge is selected for further consideration. Advanced control of such a converter has been discussed along with a conceptual controller. |
