MOSFET Efficiency

Improvements in silicon performance - including process structures that improve on-resistance and lower gate resistance (Rg) - are being combined with optimal package technology to improve the efficiency, reliability and thermal performance of next-generation power MOSFETs.

High energy prices and the increasing profile of “green” initiatives such as Energy labeling for appliances and the Energy Star 80 Plus scheme for electronic products are creating a strong pull for improvements in power MOSFETs that increase DC-DC conversion efficiency in servers, notebooks, high-end desktops and other computing, datacenter and networking applications. At the same time, end-user demands for extra functions, richer experiences and smaller dimensions require devices supporting greater power density and increased reliability.

So far, great strides have been achieved, in terms of MOSFET packaging and device design, to meet these wide-ranging demands. Coming generations of power MOSFETs will combine high performing package technology with the latest advances in silicon to take power conversion efficiency to the next level, particularly for applications that demand higher frequency operation. As well as making further improvements in areas such as On-resistance RDS(on) and gate charge Qg, new MOSFET process structures that lower MOSFET gate resistance (Rg) and improve resistance/active area (R*AA) figures of merit play an increasingly important role in delivering additional improvements to synchronous converter efficiency.

Optimizing Package Performance
Surface-mount power packages have evolved through several generations since the arrival of the first SO-8 Power MOSFETs in the early 1990s. Techniques such as double-sided cooling, large metal leadframes and clip bonding to die-level ohmic contacts have all been developed to minimize the effects of thermal resistance from junction to case (RTHj-c) and to combat electrical loss mechanisms such as Die-Free Package Resistance (DFPR) and parasitic inductances. Successful power packages include IR’s leadless Power QFN (PQFN) for small-footprint applications.

Among the most effective packages for power MOSFET design has been International Rectifier’s DirectFET®. In particular, the simplicity of the package construction, with fewer interfaces when compared, for example, with PQFN alternatives, makes DirectFET an attractive solution for applications where reliability is a primary design requirement. The latest generation of IR’s DirectFET package technology delivers close to ideal performance by combining techniques to minimize RTHj-c and reduce DFPR to a level insignificant relative to the RDS(on) of the MOSFET die. The DFPR, as well as parasitic inductances, have been successfully reduced through simplified construction, which minimizes the number of materials through which the current must pass. The cross-sectional diagram of figure 1 illustrates the features of DirectFET packaging technology, which combine effectively to minimize the key electrical and thermal parasitic effects.

As the diagram shows, the MOSFET die is fabricated with top-layer metal in conjunction with a proprietary passivation system. This creates large gate and source contacts on the surface of the die. The die is then flipped, bringing the terminals into direct contact with the PCB. A top-side copper can provides the connection from the drain on the back of the silicon die to the PCB. This construction eliminates not only the conventional lead frame and wirebonds that lead to high package resistance but also eliminates plastic packaging materials, which have relatively high thermal resistivity compared to the metals used in the DirectFET package.

Using DirectFET packaging helps to both reduce losses and heat generation in the PCB itself. The design maximizes contact area between the source and gate pads and the PCB for best electrical and thermal efficiency, while conduction of drain (load) current through the can rather than through the PCB eliminates effects of I2R losses in PCB traces. This greatly enhances overall efficiency. At the same time, the large copper drain connection provides an alternate path for heat dissipation and provides a very efficient thermal interface to an external heatsink.

In addition, the DirectFET package has extremely low source inductance (Ls), and the large gate and source terminals also allow driver circuitry to be connected without including any PCB stray inductance in the high current path. This results in exceptionally good high frequency switching performance, with improved turn-on and turn-off characteristics and low switching losses in circuits such as synchronous buck converters.

Source Inductance and Switching Loss
Low source inductance helps to reduce switching losses associated with the turn on and turn off of the ControlFET by minimizing the de-biasing effect of the common source impedance in a sync buck circuit. To highlight the benefit of the low source inductance achieved using DirectFET technology, figure 2 shows the effects of Ls when switching the control FET of a synchronous buck converter. At turn on, a voltage drop is induced across Ls as the gate drive voltage increases and the FET turns on. This voltage drop reduces Vgs, thereby impeding the turn on of the MOSFET. This increases the turn-on time of the device and hence increases switching losses.

At turn off an opposite effect is induced that causes the Vgs to increase. This extends the turn-off time and adds further to switching losses. Figure 2b shows the effect of Ls on power loss.

The DirectFET package, combined with effective optimization of the PCB layout, minimizes this effect resulting in improved efficiency and lower heat dissipation. Other parasitic inductances are also significantly lower compared to other packages, contributing to faster transitions and hence lower switching losses. These include the drain-to-source inductance (Lds) and the gate inductance (Lg). Lg is extremely low as the gate is soldered directly onto the PCB.

Next-Generation Silicon Supports Industry-Leading Performance
Clearly, DirectFET technology has enabled a number of significant performance improvements at both package and PCB levels. Improvements at the MOSFET silicon level are more difficult to achieve; processes, architectures and material technologies are already highly evolved, and it is well known that the established techniques for reducing RDS(on) to enhance conduction performance tend to increase the gate charge (Qg) resulting in higher switching losses.

With the emergence of synchronous topologies, which have improved typical buck converter efficiency, MOSFET vendors have been able to maximize these improvements by offering devices as a chipset combining MOSFETs that are individually optimized for control FET and sync FET duties. In these chipsets the control FET is optimized for minimum switching losses, while the sync FET characteristics prioritize low conduction losses.

The trade-off between RDS(on) and Qg has presented a barrier to further improvement of MOSFET performance. Development has focused on optimizing device characteristics based on [RDS(on) x Qg] as the dominant FOM for power MOSFETs. The latest DirectFET plus family of devices, however, uses new silicon structures that not only further reduce RDS(on) and Qg but also offer industry-leading RDS(on)*AA figures of merit while reducing an additional parameter that contributes to power loss, namely gate resistance (Rg).

The contradiction is due to the fact that the traditional FOM does not take into account the impact of Rg on a number of loss mechanisms, including Cdv/dt on the sync FET, gate driver and dead time.

As a practical illustration, Figure 4 shows how reducing Rg of the control FET has a dramatic effect on efficiency as operating frequency is increased from 300kHz to 800kHz.

Lowering Rg is also effective in preventing Cdv/dt induced turn-on of the sync FET. This spurious turn-on can occur due to the rapid increase in sync FET drain voltage caused by turn on of the control FET. The rapidly increasing voltage induces a voltage spike on the sync FET gate through the device’s Cgd capacitance, which can be large enough to turn the sync FET on. Although not catastrophic to the device, Cdv/dt induced turn-on incurs significant losses that are largely independent of load current and therefore impair efficiency throughout the load range. The effects also compromise the reliability of the converter.

Cdv/dt induced turn-on is typically avoided by ensuring the sync FET has a low gate-to-drain charge, Qgd and a low charge ratio (Qgd/Qgs1). Qgs1 determines the amount of charge required for the gate to move from ground to its turn-on threshold. Qgd is defined as the Cgd charge when the drain voltage rises to 15V. As a rule of thumb, a charge ratio close to 1.0 has been considered sufficiently low to eliminate Cdv/dt turn-on. However, typically a reduction in charge ratio can impact RDS(on). A lower Rg can help to compensate for a higher charge ratio, allowing low RDS(on) to be maintained without increasing the risk of Cdv/dt turn-on.

A further benefit of lowering Rg is to ensure more even turn-on of the MOSFET cells across the die, bearing in mind that power MOSFETs comprise large numbers of cells connected in parallel. Ensuring more uniform turn-on characteristics for the individual cells avoids temporarily exposing a reduced number of cells to the full load current.

Rg and Driver Selection
When the converter designer comes to select suitable gate drivers for the sync FET and control FET, a low Rg increases design freedom and allows a lower cost driver to be chosen. For the same reason that the optimized DirectFET gate connection reduces reliance on a high-strength gate driver, low impedance in the gate-drive circuit is also desirable. Using a low Rg MOSFET allows designers to match the impedance of the gate-driver output circuit with the impedance of the MOSFET gate circuit to ensure reliable, consistent switching when using a low-cost, low-power gate driver.

Further Sync FET Optimization
During sync FET turn-on, the MOSFET body diode carries most of the load current in the period before the gate voltage has reached its threshold. When the gate voltage reaches its threshold, the load current gradually transitions into the MOSFET channel. Integrating a Schottky diode with the MOSFET die effectively minimizes the diode’s reverse-recovery losses during this transition, thereby contributing to improved efficiency. The efficiency gains achieved by using a sync FET with integrated Schottky diode are greater at higher operating frequencies. This can be illustrated mathematically using the expression for power loss below, which shows how the influence of Qrr and diode conduction losses increases with operating frequency:

Ploss = (1-D)•(Irms2•RDS(On))+ ( Qg•Vg•f) + (Qoss•Vin•f)/2 + (Qrr•Vin•f) + (tDT•Iout• f •Vf)

Device Design and Evolution
As far as device design is concerned, MOSFET Rg can be reduced significantly below 1Ω with no disadvantage in terms of other loss-related parameters.

When selecting MOSFETs for high-frequency synchronous rectifiers, engineers also now need to consider the effects of Rg on converter efficiency, in addition to the conventional RDS(on) x Qg FOM. Figure 5 charts the evolution of IR’s DirectFET power MOSFETs in terms of the established FOM and the revised metric [RDS(on) x Qg x Rg]. The product is proposed as a new FOM to guide the design of high-frequency synchronous converters in the future.

Combined Strengths
The efficiency advantages of low Rg MOSFET is amplified further when combined with DirectFET package technology. Since a higher Rg tends to mitigate the switching speed advantages resulting from DirectFET’s low gate inductance, a MOSFET with low Rg (less than 0.5Ω) will switch at high speed with lower gate drive when packaged in a DirectFET compared to an alternative such as PQFN. This can save engineers from having to specify a very strong driver, thereby enabling cost and power savings.

IR has combined these technologies in its latest DirectFET plus family of MOSFETs, enabling power supply designers to continue increasing the efficiency of synchronous converters for use in consumer and professional equipment spanning a variety of power ratings.

Figure 6 shows the efficiency achieved using a two-phase synchronous converter built using the IRF6811/IRF6894 DirectFET plus chipset. The 12V to 1.5V converter achieves peak efficiency of 94.5% when operated at 300kHz with no heatsink, showing how designers can achieve new standards of efficiency for power supplies in the 100W range.

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