Performance vs power in off-chip DDR SDRAM
Memory-system management reduces dissipation while meeting application-performance demands
To deliver new features and higher performance in consumer-electronic products, SoC developers constantly look to integrate more functionality into their designs.
SoCs with more features and performance typically operate with higher clock frequencies, which require faster access and greater bandwidth to memory. DDR (double-data-rate) SDRAM, the most cost-effective off-chip memory, is the memory of choice to meet the increasing bandwidth needs of today’s SoCs.
DDR-SDRAM subsystems offer cost and performance benefits, but higher performance usually translates to increased power consumption. Whether the design is for mobile or wired applications, it is critical that designers optimize their DDR-SDRAM subsystems to manage power consumption while maximizing system performance. Designers can build a complete DDR subsystem that balances power and performance requirements by drawing on their application knowledge and taking advantage of available DDR SDRAM power-management features.
Issues for mobile products
Power management is a primary concern in mobile-product designs because battery capacity limits the product’s available source energy. The less power the product consumes, the longer it can operate before the user must recharge the battery. Even though battery technology is dramatically improving, the desire to support multi-tasking applications increases the power requirement. Multi-tasking applications demand higher bandwidth from the DDR-SDRAM subsystem, which often translates to a faster clock rate that requires more power.
Mobile products do not operate constantly, so power management targets two areas: active power (power consumed while the product is in use) and standby power (power consumed while the product is on but inactive). Because of the sensitivity to both active and standby power, mobile products typically use low-power SDRAM such as LPDDR2 (low-power DDR2) or LPDDR3 (low-power DDR3). Low-power DDR SDRAM consumes less power in active mode. For example, the low-power variants forgo the common parallel termination mainstream DDR2 and DDR3 devices use. They also reduce power in standby mode by, for example, forgoing the on-chip DLL (delay-locked loop) that standard DDR memory includes.
In contrast to LPDDR3 SDRAM, mainstream DDR3L memory consumes slightly more power for the same operating frequency in active mode but approximately nine times more power in standby mode (Figures 1 and 2). Between LPDDR2 and LPDDR3, several features support the low-power requirements of mobile products including low I/O supply voltage, PASR (partial array self-refresh), and deep power down. Mobile SoC developers leverage these and other LPDDR SDRAM features to minimize power in the SDRAM interface.
Low I/O supply voltage: Switching power in CMOS chips is directly proportional to CV2f where C is the capacitance of the switching node, V is the voltage swing, and f is the operating frequency. Due to its square-law relationship to power dissipation, reducing the voltage swing has the greatest potential to reduce power consumption. As a result, LPDDR2 and LPDDR3 SDRAMs offer a low I/O supply voltage of 1.2 V as compared to DDR3 SDRAM’s 1.5 V or DDR3L SDRAM’s 1.35 V.
PASR: Because their data is stored on small capacitors, SDRAMs require periodic refresh operations to maintain their data integrity. Self-refresh is a mode that puts the SDRAM into a low-power state and the device manages its own refresh requirements to maintain data integrity without intervention from the memory controller. SDRAMs that support PASR allow the system to determine if it needs to maintain all of data stored in the SDRAM or if only a portion of the entire SDRAM needs to be refreshed. Since any refresh operation consumes power, excluding parts of the SDRAM from self-refresh saves overall system power. Both LPDDR and LPDDR2 SDRAM support PASR.
Deep power down: Mobile products can also take advantage of the deep-power-down command in low-power SDRAMs. Designers use deep power down when the SDRAM does not need to retain its contents and when the system can handle a longer than normal activation cycle. In deep power down mode, the LPDDR SDRAM can disconnect all internal power from within the memory and will consume the least amount of power as compared to all other modes.
Issues for wired products
Power management is also an issue for wired systems including HD TVs, set-top boxes, computers, and other products that draw power from a wall outlet. Power consumption affects wired consumer products on two fronts: cost and conformance to national or international regulations.
To be competitive, consumer products need to be available at the lowest possible cost. Systems that consume more power often require advanced packaging to dissipate the heat chips generate and may require cooling elements such as heatsinks or fans, increasing total cost. LPDDR SDRAM is not a good option for non-mobile consumer devices because it is more expensive compared to mainstream DDR SDRAM and it typically cannot support the performance requirements those products impose. Therefore, wired devices usually use mainstream DDR SDRAM such as DDR3.
DDR3 SDRAM does not support as many power saving modes as LPDDR SDRAM because the target use model typically has not been as sensitive to power as mobile devices. In addition, DDR3 SDRAMs are often in systems with 8 to 16 SDRAMs requiring features such as on-chip DLLs and ODT (on-die termination) to accommodate the large number of SDRAMs driven by one controller. DDR3 SDRAM supports both active power-down and precharge power-down modes. The SDRAM disables its on-chip DLL during precharge power-down and consumes less power than in active power-down, which doesn’t disable the DLL.
DDR power options
Although DDR SDRAM’s power features can help reduce memory-subsystem dissipation, the realized energy savings typically are not sufficient to be competitive. To improve power management of a DDR subsystem further, SoC and system designers can leverage their knowledge of how their system accesses the DDR SDRAM.
Designers can apply active and standby power-management techniques to DDR SDRAM subsystems. These techniques can apply to both mobile and wired applications.
Active power management: To determine the best active power-management structure for a DDR subsystem, recall the switching power determined by the CV2f relationship. The capacitance is usually fixed so designers focus on how to manage the voltage, which has a squared contribution, and the frequency, which contributes linearly.
The largest consumer of active power is the I/O interface, which drives commands and data off-chip during write operations, and receives data during read operations. Designers can reduce power consumption by using DDR3L instead of DDR3, which will cut the voltage from 1.5 V to 1.35 V, saving nearly 20% of the memory device’s power .
In addition to I/O voltage reduction, system designs can reduce active power by scaling the operating frequency. Part of the drive for more performance is that consumers are demanding more capabilities in electronic products. Not all of these applications operate all the time, nor do they often operate simultaneously. Additionally, not all of the applications require the same amount of bandwidth from the SDRAM. Conceptually, designs can add intelligence to a DDR SDRAM subsystem that will manipulate the operating frequency depending on the running applications’ bandwidth requirements. Through frequency scaling, a DDR SDRAM subsystem can consume less power (Table 1). Systems can implement frequency scaling in either low-power or mainstream DDR SDRAM but it is favored in low-power SDRAM due to its lack of an on-die DLL.
Standby power management: When a modern consumer product connects to its energy source, it is always consuming some power. Even if an SoC stops reading and writing data to SDRAM, it still consumes power, albeit at a lower rate. Reducing this standby power is the second type of power reduction and requires other system power-management techniques.
One technique removes the power from your chip or SDRAM interface by disconnecting the source. When power removal is a practical option, the system must be capable of controlled and rapid power switching. In addition, the system must be able to pick up where it left off so as not to consume unnecessary time cycling through an entire power up sequence.
Features for power reduction: Certain power-reduction techniques depend on feature support in the DDR controller and PHY (physical layer). SoC designers must understand the bandwidth demands each of the IC’s applications impose, and then leverage these techniques to architect a lower-power system.
For example, in frequency scaling, the DDR controller and PHY must be able to communicate with each other to manage the frequency transitions. Likewise, when enabling system power shut down, the controller and PHY provide the appropriate handshakes to ensure the complete DDR SDRAM interface operates appropriately throughout the different modes. Therefore, not only must the DDR controller and PHY support these modes, but their implementations must be mutually compatible. This typically occurs only when the complete DDR interface IP comes from a single supplier and the memory controller can interoperate with the PHY to optimize performance and power conservation.
A complete, integrated DDR subsystem can support other power-management techniques as well. For example, a tightly integrated DDR controller and PHY can leverage the controller’s look-ahead capability to manage the PHY’s power intelligently by enabling and disabling certain PHY functions and capabilities at appropriate times.