2014 Symposia on VLSI Technology & Circuits to highlight latest in microelectronics

Date
04/25/2014

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The latest advancements in microelectronics technology and circuits will be presented by the world’s leading experts as they gather for the 2014 Symposia on VLSI Technology and Circuits, from June 9-12 (Technology) and from June 10-13 (Circuits) in Honolulu, Hawaii. Alternating between Hawaii and Japan each year, the Symposia represent the semiconductor industry’s most significant mid-year conferences for the latest research in many key technology areas.

A single registration fee enables attendees to participate in both symposia and benefit from this unique opportunity for interdisciplinary learning between device technologists and circuit/system designers. The technical programs of both Symposia overlap, with key topics organized into several Joint Focus sessions.

Preceding each Symposium are full-day short courses featuring distinguished international speakers from industry and academia; evening rump sessions spanning a range of thought-provoking issues that face the industry; and a joint banquet to provide an informal atmosphere for the exchange of interdisciplinary ideas. Also preceding the Symposia will be two satellite workshops: IEEE’s Silicon Nanoelectronics Workshop on June 8 & 9; and a workshop on Spintronics on June 9.

“CMOS scaling down to the 10-nm node, implementation of FinFET, FDSOI and quantum well structures, and novel memory technologies highlight the Technology program,” said Klaus Schruefer, Intel Mobile Communications, chair of the 2014 Symposium on VLSI Technology. “In addition, the potential to use silicon photonics as a memory interconnect technology will be demonstrated, along with a novel curved CMOS image sensor.”

“Significant advancements in diverse application areas such as wearable medical electronics, wireless sensor networks and data-encryption/security circuits are among the highlights of the Circuits program,” said Vivek De, Intel, chair of the 2014 Symposium on VLSI Circuits. “Power management and energy efficient circuits, along with wire-line and optical communication systems, will also be demonstrated.”

Full-day Short Courses
VLSI Technology Short Course (June 9)
- “High Performance Mobile SoCs: Enabled by 10nm SoC Technology” -- This course will comprise 8 lectures given by distinguished speakers, covering such topics as SoC applications, FEOL & BEOL scaling & design technology co-optimization, memory platforms (eSRAM, eNVM, and eDRAM). Details and registration information can be found here: http://www.vlsisymposium.org/vlsi-technolog/
VLSI Circuits Short Courses (June 10) –
- “Advanced Data Converter & Mixed-Signal Circuit Design” -- This course covers A/D converter trends, SAR ADCs and CMOS scaling, as well as wire-line, wireless and optical communications technologies.
- “Advanced Energy Efficient Digital Design.” -- This course covers low-power CPUs, energy-efficient architectures, ultralow voltage logic design techniques and advanced SRAM designs.

The Circuits short courses are offered as two parallel full-day sessions, given by 12 expert international speakers from industry and academia. A single registration fee covers both courses, and participants can switch between the two.

VLSI Symposia Technology/Circuits Joint Focus Sessions
The Technology/Circuits Joint Focus Sessions are a key element in the unique interdisciplinary environment the Symposia provides to advanced device and circuit design co-optimization. They are:
3D Circuits & Applications (Session C4, Wednesday June 11)
3D Systems & Packaging (Session T14, Wednesday June 11)
Design/Technology Co-Optimization II (Session T17, Thursday June 12)
Non-volatile & Emerging Memory (Session C12, Thursday June 12)
SRAM & DRAM (Session C14, Thursday June 12)
In addition, the Symposium on VLSI Technology will hold two special focus sessions on “Embedded NV Memory Technologies” (Session T5) and “Interconnect: Local & Global” (Session T16).

Plenary Sessions
Two invited plenary talks open the Symposium on VLSI Technology. First, Robert Aitken, ARM Fellow, will address: “Device and Technology Implications of the Internet of Things,” a discussion of the challenges posed by the greater connectivity and the trust, security and service components of this increased interactivity. Then, Keiichiro Shimada, senior vice president of Sony Corporation will present “Customer Value Creation in the Information Explosion Era,” a discussion of the impact of semiconductor technology on consumer electronics and information industries in the still rapidly expanding pace of communications.

Opening the Symposium on VLSI Circuits will be two invited plenary talks by renowned experts, starting with “Data Center 2020: Near-memory Acceleration for Data-oriented Applications,” given by Ed Doller, vice president & chief memory systems architect of Micron Technology. He will discuss the challenges of developing the data search and advanced memory technologies needed for tomorrow’s computing infrastructure. The second plenary talk, “Technology Development for Printed LSIs based on Organic Semiconductors,” will be given by Jun Takeya, professor at the University of Tokyo. He will focus on recent printed LSI developments for low cost platforms in RFID, data processing and sensor; as well as new organic semiconductor materials. Details for both Symposia plenaries here: http://www.vlsisymposium.org/plenary-rump-sessions/
Evening Rump Sessions

As part of the Symposium on VLSI Technology a rump session is scheduled on Tuesday evening, June 10 to foster open discussion of important industry issues: “450mm, EUV, III-V, 3D – All in 7nm? Are You Serious?!” moderated by Andrzej Strojwas of PDF Solutions, will explore the challenges of simultaneously mastering multiple technology and manufacturing disruptions as the semiconductor industry moves away from the proven silicon channel to the future materials in III-V and/or Ge-based transistors; as well as EUV lithography, chip and wafer stacking, and the ever-present cost reduction pressures.

A joint rump session sponsored by both Symposia will be held on Tuesday evening: “Who Gives Up on Scaling First: Device & Process Technology Engineers, Circuit Designers, or Company Executives? Which Scaling Ends First – Memory or Logic?”-- The session will give the audience an opportunity to explore the timely issue of who will drive the decision to stop CMOS scaling, in the context of technology challenges, manufacturing infrastructure, circuit design and cost issues. Moderated by Elad Alon of UC Berkeley and Yee Chia Yeo of National Univ. of Singapore, it will include expert panelists from Intel, NVIDIA, Qualcomm, Renesas, Sandisk, SK Hynix, UC Berkeley, and TSMC.

The Symposium on VLSI Circuits also will hold two parallel rump sessions, on Thursday evening June 12: “Lessons & Challenges for Future Mixed-Signal, RF & Memory Circuits” will feature expert panelists from Analog Devices, Intel, Micron, Oregon State University, Samsung, Tokyo Institute of Technology, UCLA, and University of Twente addressing the key bottlenecks in achieving first-silicon success, as well as 3D/2.5D interconnect challenges.

“What Should Circuit Designers Do In an Era of System Level Design” Panelists from AMD, MediaTek, Qualcomm, Samsung, UC Berkeley, Waseda University, and Xilinx will discuss whether VLSI design will be confined to a niche market or continue to play an integral role in the system design process.

Executive Panel Discussion
Thursday afternoon’s luncheon will feature an exciting panel discussion on “Emerging Semiconductor Industry Trends and Implications.” Moderated by Dan Hutcheson, CEO of VLSI Research, Inc., the panel will include senior industry executives from Micron, Applied Materials, IBM, TSMC, TI and Panasonic discussing the emerging technology trends beyond traditional scaling that are shaping the industry around us. The panel will deliberate on this topic and discuss trends, applications, industry needs, infrastructural/manufacturing gaps and economic challenges. Details on the Executive Panel Session are here: http://www.vlsisymposium.org/program/
VLSI Symposia Gets Social

Tuesday evening, June 10, will feature a joint reception sponsored by both Symposia, and on Wednesday evening, June 11, a joint banquet will be held to provide an informal, relaxed atmosphere for information exchange between technologists and circuit designers.

The Symposium on VLSI Technology

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