Docea Power software solutions
Docea Power, a provider of system level power and thermal exploration solutions, will reveal two of their latest products at the 51st Design Automation Conference (DAC). Docea Power will demonstrate the ThermalProfiler, a software solution for fast thermal exploration and verification, and the Aceplorer Power Intelligence platform (Aceplorer PI) to secure and speed-up power oriented decisions.
The Aceplorer PI platform is an innovative solution to capitalize and turn power data into an asset across and beyond functional organizations. It significantly improves the decision process by providing simulation data for multiple scenario and system configurations. It enhances productivity through a power-oriented collaborative platform offering features like exploration, versioning and automated reporting from a single user interface. The scalability is supported by a big data infrastructure.
The solution is targeted at HW/SW power architects and power-influenced decision makers who need to manage multiple SoC or platform projects and derivatives. The Aceplorer PI platform uses the paradigms developed for business intelligence solutions and applies them to system level power modeling and simulation.
The ThermalProfiler is a new solution to explore various thermal and floorplans configurations and then simulate dynamic power traces coming from other tools or measurements. It addresses the need for more interactivity between thermal experts and design teams. For an increasing number of thermally constrained devices a larger number of what-if analysis simulations are needed that require fast coupled power and thermal simulations in the time domain. The ThermalProfiler can be used by both thermal experts and system architects or power lead engineers to achieve specification and to speed up verification.
In addition, Docea Power solutions for thermal modeling will be presented in the following events during the conference:
DESIGNER TRACK SESSION 16: Thermal Modeling Methodology for Fast and Accurate System Level Analysis. Application to a Memory-on-Logic 3D circuit.
When/Where: Tuesday, June 3,, 2014 from 10:30am to 12:00pm, room 105
Who: Pascal Vivet, CEA-LETI, Grenoble, France
SESSION 6W WORKSHOP: DAC Workshop on System to Silicon Performance Modeling and Analysis
TRACK: EMBEDDED SYSTEMS, TOPIC AREA: EMBEDDED SYSTEM DESIGN,
When/ Where: Thursday June 05, 9:00am - 5:00pm | Room 202
Who: Gene Matter, Sylvian Kaiser, Docea Power, San Jose, CA, Moirans, France
When/Where
Monday-Wednesday, June 2-4, 2014, 9 am to 6 pm
Docea Booth #2223
Moscone Convention Center, San Francisco, CA
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