Put Speed into Your Product Development - USB-PD Solutions: Part 3 of 4

Gautam Chinagundi, Staff Specialist Product Marketing, and Rashed Ahmed of Infineon Technologies


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Novel cost-effective USB-PD solution with the EZ-PD™ PAG1 series

Figure 1: Two-chip power adapter solution using PAG1S and PAG1P

Avoid complexity, incompatibility and shorten time-to-market! Infineon with its broad portfolio of high-performing and high-quality USB-PD solutions help engineers break through the barriers in fast charging designs at a competitive cost

The need to charge the devices in the shortest amount of time is driving the consumer power adapter market towards fast charging adapters. On one hand, the power delivered by these adapters is increasing while on the other hand, their sizes are getting smaller in order to provide a better end-user experience thereby pushing the manufacturers to build higher power density designs.

There are multiple fast charging standards in the market which are evolving and continuously upgrading in order to become better and more secure. To address this increasing demand for high power density fast charging adapters, Infineon offers the PAG1 solution, a complete AC-DC power solution with an integrated USB Power Delivery (PD) controller. It is a two-chip USB-C power adapter solution which comprises of a primary start-up controller (PAG1P), and a single-chip secondary-side controller (PAG1S). PAG1P and PAG1S together operate in a secondary-side controlled flyback architecture. PAG1P provides the start-up function, drives the primary FET, and responds to fault conditions. PAG1S is a single chip secondary-side controller that integrates the synchronous-rectification controller, PD controller, PWM controller, a 30 V regulator, high-voltage NFET gate drivers, and protection circuitry.

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Figure 2 Block diagram of a secondary-side controlled power adapter using PAG1S and PAG1P


Typically, an SMPS operates as a voltage regulator. This means a feedback link is needed from the output to control the power stage. The control loop compares the output voltage against a reference voltage to generate the PWM signal to drive the primary switch and thereby regulates the output voltage. In the commonly used primary-side controlled architecture, an optocoupler is used as a feedback link to transmit an error signal from the secondary side to the primary controller. However, such an architecture has limitations. Firstly, Optocouplers have limited loop bandwidth. Hence, their use in the feedback loop makes it difficult to achieve a fast dynamic load response and maintain higher gain/phase across a variable output voltage. Also, the loop bandwidth and gain degrade over time. Secondly, every output related function needs to be communicated over the isolation barrier to the PWM controller. This adds lag time, thereby increasing the subsequent time needed to make the necessary adjustment to the PWM controller. Output related function can be attributed to, output current protection, overvoltage protection, undervoltage protection, load sharing, driving synchronous rectifiers, and so on.

To overcome the shortcomings of a primary-side controlled architecture, Infineon offers the PAG1 solution using a secondary side-controlled architecture. In this design, the regulation happens on the secondary side with PAG1S and the primary controller (PAG1P) acts as a simple gate driver. This combo achieves isolation between the primary and secondary side using a pulse transformer. The brain of the converter sits on the secondary side (PAG1S) where all decisions related to the output voltage regulation that make the control loop faster are made. Also, this architecture enables immediate reaction to any malfunction on the secondary side, thereby making the system more robust. By not using an optocoupler, the system behavior is more consistent and predictable from unit to unit over operating point, temperature and product lifetime.

The secondary-side controlled architecture also enables direct control of the SR FET in a way that achieves zero voltage switching (ZVS). ZVS enables higher efficiency on an existing converter without the use of any extra circuitry. With the ability to support higher loop bandwidth and faster dynamic response times, the secondary-side controlled architecture is best suited to support higher switching frequency thus higher power density designs. One issue with secondary side controlled architecture is the initial power-up to jump start the circuit by using an extra power supply. We overcome this issue with PAG1P. PAG1P helps power up the secondary side during startup. Once the system reaches the steady-state operation, it transfers the control to the secondary side and acts only as a primary-side gate driver with primary-side fault protection (OVP, UVP and OCP).

The PAG1S is a programmable device and as such allows for great flexibility in power adapter designs. The user can adjust the QR valley at which the converter switches across line/load and thereby optimize the system efficiency without changing the external hardware components. EZ-PDTM configuration utilitytool allows the user to easily fine-tune the value of the current sense resistor to account for the variations seen due to board designs without changing the hardware. The tool also offers the flexibility to configure the fault protection thresholds and the recovery mechanisms for overcurrent protection (OCP), overvoltage protection (OVP), short circuit protection (SCP), and overtemperature protection (OTP). In addition, the PAG1S can be re-programmed on the field to cater to the latest USB-C PD standard or to address any newly discovered post-production bugs.

Increasing needs for short charging times have led to multiple fast charging standards in the market such as Adaptive Fast Charging (AFC), Quick Charge (QC), Apple 2.4 A charging, Huawei FCP/SCP, or USB-C power delivery. Hence, retail manufacturers will hold a competitive edge if they can support multiple protocols on the same device. The PAG1 solution enables this by supporting AFC, QC4+, QC4, QC3, Apple 2.4A charging and BC1.2 all on the same device with no additional bill-of-material (BOM) cost. In addition, PAG1 offers enough Flash to implement other proprietary protocols defined by the customer with Infineon supporting the Firmware development and compliance.

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Figure 3 A 65 W reference design using PAG1S and PAG1P in a 52 mm x 42 mm x 22 mm board


To enable faster time to market and cut down on the development costs, multiple PAG1-based reference designs are available across power levels. They come in competitive form factors and are tested as per the standards defined by DoE Level VI, CoC Tier 2, USB-C PD and CISPR 32 Class B.  More details on the reference designs along with the validation reports can be accessed under https://www.cypress.com/products/usb-type-c-and-power-delivery.

Discover more reference designs, boards and design support documents at www.infineon.com/usb-pd!

** Please note that Cypress is an Infineon Technologies Company. The article includes refernces to the Cypress webpage as this is the company that originally developed the product. Please also note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio.