Advanced simulation tools accommodate fabrication tolerances

Process, device, and circuit simulation tools are essential for reducing time to market and the cost of new microchip technology developments, delivering faster computers, better consumer products and fueling the digital economy. The ITRS (International Technology Roadmap for Semiconductors) estimates that the use of such tools reduces development chip times and costs by about 40%. Advanced semiconductor devices and circuits are increasingly affected by different kinds of variations which occur during the process of chip fabrication. Within the SUPERTHEME European project , a tool chain for the simulation of the impact of process variations on the devices, circuits and systems fabricated will be developed. This allows the semiconductor industry globally to minimize the detrimental effects of such variations on chips used e.g. in computers, tablets and mobile phones. CMOS process variability includes both systematic variations caused by equipment settings and inhomogeneities, which cannot be controlled with enough accuracy, statistical variations which are for instance caused by the discreteness of charge and the granularity of matter in nanometer scale transistors. Effects from various process variation sources, systematic and stochastic, influence each other and lead to variations of the devices, interconnects, circuits, in their electrical, thermal and mechanical behaviour. This presents a major challenge for the continued scaling of transistor dimensions and the increase complexity and functionality of computer chips which are essential for the economic success of the semiconductor industry. Correlations between different effects of variability are of key importance because they drastically affect production yield and the performance of chips and corresponding consumer products. Where the comprehensive experimental investigation of these effects is largely impossible, suitable simulation tools offer the possibility to predict the effect of process variations on subsequent process steps and on the behavior of final fabricated devices and circuits. This important application of simulation is, among others, highlighted in the ITRS. The SUPERTHEME consortium will address, and remove most problematic weaknesses that limit use of current simulation software to study the influence of both systematic and stochastic process variability, and its electro-thermo-mechanical interaction effects. With particular emphasis being put on the study of correlations, as their treatment needs to be an essential feature of the ultimate simulation system. The project will efficiently combine use of commercially available software and leading-edge background results of consortium partners with research, development and implementation of the key missing elements bridging the current critical gap between variability simulation at the process and device/interconnect level. The capabilities of the software system will be demonstrated on advanced analog circuits as well as on aggressively scaled digital CMOS technologies. To reach these ambitious goals, a consortium of European companies active in complementary fields and leading European research institutes and Universities has been formed, covering a wide range of expertise from semiconductor equipment and technology to modelling, simulation, and finally industrial exploitation. On October 2, 2012, the project coordinator, Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. hosted the start-up meeting for the three year project which has a total budget of €4.79m. The other members include ams AG, Technische Universität Wien (Austria), Gold Standard Simulations Ltd, University of Glasgow (UK) ASML Netherlands B.V. (Netherlands) IBS and Excico France (France) and HQ-Dielectrics GmbH (Germany).