Altera, now a part of Intel, announced its participation at Embedded World 2016 during which the company will showcase a range of Altera and partner technology demonstrations at their stand in Hall 5. These will include a wide range of applications including industrial automation for smart factory “Industry 4.0”, SIL3 functional safety, Qt5.x/OpenGL compliant graphics cores, real-time optical character recognition, video/vision processing and analytics. In addition, there will be a demonstration of an ADAS stereo vision video analytics application at the Intel stand in Hall 1, stand 338.
In collaboration with partner Exor International, the smart factory exhibit will focus on enablement for the Industrial Internet of Things (IIoT) and will feature multiple single-chip high-end programmable logic controllers linked via an Industrial Ethernet interfaces and a Time Sensitive Network (802.1 TSNn) using IP from another Altera partner TTTech.
The real-time optical character recognition demo uses a low-cost machine vision camera connected directly to an Altera SoC FPGA device to receive data from a sensor, pipe it directly to memory and format it in such a way that it can be read from a Linux video application running on the SoC’s ARM processor. The Halcon software library is used to recognize hand written characters in the image.
Partner TES Electronic Solutions GmbH will demonstrate their D/AVE NX core solution that provides HMI framework support such as Qt 5.x, WebGL (HTML5) and Android on Altera Cyclone V, Arria 10 and Stratix 10 SoC devices. The set-up will preview D/AVE NX capabilities and a Qt user interface with a native OpenGL ES 2.0 application.
On Wednesday 24th February at 4pm (Workshop session 22), Altera’s partner Yogitech will be presenting a paper titled “Providing Functional Safety and Security for Multicore Systems”. This will introduce the requirements of functional safety standards related to multicore applications, IEC 61508, ISO 26262 and the upcoming ISO 19451 (the outcome of ISO 26262 semiconductor working group). This presentation, and their demonstration on the Altera stand, features Yogitech IP that allows users to design dual core lockstep Nios II processor systems.
