Ally Winning, European Editor, PSD
#transistors #FinFET #digitaldesigner #psd #validationtools #psd
In some ways digital designers have it easier than their analogue and mixed signal compatriots. They have many more tools at their disposal to verify and validate designs before they go to fabrication, which can bring a reasonable measure of assurance that they have their design right, as well as tools that can predict how the design will wear with age, or under thermal stress. With analogue and mixed-signal chips growing more complex, and being used heavily in mission-critical applications, designers now require not only an assurance of performance, but that that performance can be sustained over a specified period of time in a wider variety of environments.
For these mission critical applications, designers need to have the confidence that analogue and mixed-signal designs will operate over the whole product lifecycle in a variety of challenging conditions and that faulty die and test escapes can be found as early as possible in the process, thermal overstress can be prevented during everyday use and variations in process don’t affect device degradation throughout the entire useful lifetime.
Many of the digital verification and validation tools are made by Cadence, and now the company has a new product that will be useful to analogue designers. The Cadence Legato Reliability Solution is designed for industries where reliability is critical, such as the aerospace, medical and defence industries. The tool can help analogue developers predict the performance of their designs throughout the product’s lifecycle and under different conditions.
The Legato Reliability Solution is based on two of Cadence’s other products, the Spectre Accelerated Parallel Simulator and the Virtuoso design platform and it provides analogue defect analysis, electro-thermal analysis and advanced ageing analysis.
To provide analogue defect analysis, Cadence has included a simulation engine that expands test capabilities beyond traditional functional and parametric testing. The testing allows designers to find and eliminate die that have manufacturing defects and find die with the test escapes that can cause field failure. The tool also help eliminate overtesting.
The tool’s dynamic electro-thermal simulation engine allows the simulation of temperature rise on the chip and validates the correct operation of over temperature protection circuits.
Enhanced ageing analysis is included to simulate the effects that can accelerate the wearing out of devices, including process variation. The new feature also has a new model that can estimate the ageing effects of FinFET transistors. The accurate simulation of ageing should allow designers to reach lifetime targets without excessive over engineering.
With these three features, analogue designers can gain some of the confidence in design operation throughout the whole product lifecycle that digital designers often take for granted.