Author:
Carrie Browen, Keysight Automotive
Date
12/23/2025
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Figure 1: SerDes, like other technologies, uses an OSI model to define the interactions between layers. All layers of the stack are required for the system to function properly
As intelligence shifts into software, vehicles gain scalability and flexibility but also face new challenges in E/E architecture design. With sensors and displays generating terabytes of data daily, faster networks and high-performance computing are essential. Emerging SerDes standards, such as OpenGMSL, offer promising solutions; however, their effectiveness depends on well-defined test methodologies and compliance frameworks to ensure interoperability and reliability.
To support the rollout of OpenGMSL, the industry is actively working towards the development of a formal Compliance Test Specification (CTS). This CTS will define the test modes, limit lines, and methods of implementation (MOI) necessary to validate performance and interoperability across vendors. It will also enable engineers to quantify margin and make informed trade-offs. This is especially critical in automotive environments, where signal integrity, EMI resilience, and functional safety must be validated under real-world conditions.
While the development of a CTS for OpenGMSL is still underway, the approach draws on proven methodologies from other high-speed digital domains. The goal is to create a scalable and vendor-neutral test ecosystem that supports innovation and interoperability in next-generation automotive networks.
Why Standardization Matters
Standardization in testing is not just about compliance; it’s about enabling scalability, reducing cost, and accelerating innovation. A well-defined test specification allows:
Formal compliance programs that ensure interoperability across silicon, Tier 1 suppliers, and OEMs
The 7-layer OSI model is a foundational framework for defining communication networks. It provides a structured approach to interoperability, enabling complex systems to communicate seamlessly. While the OSI model is generalized, each technology implementation adapts it to meet specific application requirements. Despite these variations, the principle remains constant: each layer depends on the proper functioning of the layers beneath it.
When we examine SerDes standards, essentially, the OSI model effectively ends at the native protocol layer. Below that, an adaptation layer handles the packetization of data to and from the native protocol. At the data link layer, physical lanes are mapped to multiple logical ports, enabling efficient data transmission to and from the physical layer.
As with any standard, the initial focus is on the physical layer, specifically below the Physical Coding Sublayer (PCS) and above the Medium Dependent Interface (MDI). Depending on the measurement plane definition, this may involve the Physical Medium Attachment (PMA) or Physical Medium Dependent (PMD) interface.
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Figure 2: A view of how the SerDes-specific OSI model is adapted. Adaptation to and from the native protocol involves packetizing the data, while at the data link layer, physical lane is mapped to and from multiple logical ports
At the physical layer, compliance means meeting specific signal quality metrics at the transmitter, such as power spectral density, jitter, and signal-to-noise and distortion ratios. At the receiver, this involves maintaining bit error ratios within defined thresholds to prevent error propagation into higher layers such as the data link or native protocol. These requirements imply advanced equalization, clock recovery, and error correction techniques, all of which are central to the technology and design.
Lessons from Ethernet and Beyond
Ethernet’s evolution in automotive is a case study in successful standardization. By defining dedicated physical layer specifications, compliance tests, and interoperability requirements, Automotive Ethernet has established itself as a reliable backbone for in-vehicle networking. And Automotive Ethernet has been modeled from other industry examples, such as Peripheral Component Interconnect Express (PCIe), USB, and Double Data Rate Synchronous Dynamic Random-Access Memory (DDR SDRAM)[OpenGMSL Association Official Site]. This has enabled standardized testing and fostered robust ecosystems where multiple vendors can confidently develop interoperable components.
Let’s consider DDR as an example. There have been numerous iterations that have increased speed and reduced power consumption, each accompanied by additional challenges, including reduced design margins, signal integrity, and interoperability.
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Figure 3: The Physical layer is the primary target for the initial test specifications in any new standard, either in the PMA or PMD, depending on the definition of the measurement plane
Examining the benefits of standardizing DDR and LPDDR:
- Scalability: Enhances performance and efficiency, enabling faster data transfer and higher bandwidth compared to older or proprietary versions.
- Adaptability: Standardization creates a flexible technology stack that supports continuous improvement and evolution without frequent replacements. Backward compatibility is often included as a benefit.
- Interoperability: Provides a common framework for testing across manufacturers and systems, simplifying integration by ensuring compatibility.
- Efficiency: Reduces the time and resources required for testing, allowing for quicker development cycles and faster deployment of new products.
- Quality Assurance: Uniform testing standards help maintain high quality across the industry, minimizing defects and failures.
- Futureproofing: Ensures memory systems are designed to accommodate future technological advancements and evolving requirements.
- Consistency: Ensures that testing is conducted uniformly across different environments and devices, leading to consistent results and performance metrics.
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Figure 4. A visual example of how contributors across the industry work together to develop robust testing frameworks
The evolution of DDR and LPDDR has necessitated the development of advanced testing strategies to manage shrinking margins and complex signal environments. These methodologies, built through years of collaborative work in standards
organizations, have become foundational to ensuring interoperability and performance. Today, they offer a blueprint for testing emerging SerDes technologies in automotive systems.
Engineering Challenges in Automotive Environments
While there are many similarities between data centers and the automotive environment, there are also unique challenges and risks that arise from it.
These challenges require precise, repeatable, and scalable test methodologies, ideally vendor-agnostic and rooted in industry standards. It is not hard to understand that identifying and defining the extreme and dynamic nature of environmental noise sources in a vehicle is one thing. Recreating them in a testing environment to prove the robustness of the device's physical layer is another matter entirely. It is also important to remember that the cost of failure in automotive applications is significantly higher compared to the loss of frames in a PCIe or DDR data center example.
As OpenGMSL moves toward broader adoption, a robust CTS will be essential to ensure consistent performance and interoperability. By leveraging lessons from other high-speed digital domains, the automotive industry can build a scalable, reliable test ecosystem that supports the next generation of software-defined vehicles.
Anticipating What’s Next
The future of in-vehicle connectivity will be defined by:
To support this future, we look to embrace standardized testing as a foundational element of vehicle architectural and E/E design. Whether validating PAM-N signal linearity, ensuring compliance with ISO 26262, or correlating measurements across vendors, the goal remains the same: build reliable, scalable, and secure communication systems for the next generation of vehicles.
