Combining security and power efficiency

Author:
Shakeel Peera, Microsemi

Date
02/14/2015

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Power management is critical in hyperconnected systems

In today’s increasingly hyperconnected world, it is essential that all new designs minimize power consumption and are protected from being cloned, reverse engineered, or tampered with in order to protect embedded intellectual property, system data, and the system itself.  FPGAs play a key role in meeting these objectives. 

On the power front, FPGAs enable today’s high-speed, DSP-intensive system designs by delivering not only the lowest possible static power, but the lowest total power, as well, especially at lower frequencies and high temperatures.  This requires a comprehensive approach encompassing process technology, architecture, and the design of configurable logic, as well as the inclusion of embedded features including SerDes, DDR2/3 and DSP blocks. 

On the security front, FPGAs are delivering advances in device security by making base-level security easy to use and adopt by system architects. As FPGAs with embedded processors becoming the core of the new systems, the ideal solution is to provide SoC FPGAs with leading-edge embedded security that works inherently, and allows the system architect to plan its security architecture at the core level rather than as an afterthought. 

 FPGA advantages

Technology companies developing products for the hyperconnected world typically rely on one of the following three fundamental design methodologies to incorporate required functionalities into one or more highly-integrated devices: application-specific standard products (ASSPs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs). 

While ASSPs are frequently an ideal solution for a new design, developers cannot always find an ASSP-based solution that encompasses all the required functions for a new design on a single device.  Additionally, companies that are designing the latest ASSPs are interested mostly in very high-volume applications to amortize their extremely high-cost of ASSP development.  This leaves many applications without a “so-called” off-the-shelf ASSP solution.

ASICs have also traditionally been excellent solutions for single-device integration, but as the industry moved toward smaller geometries, overall design cycle times and high tool and other costs have prevented their use.  Designers have been forced to look for other methodologies to solve their complex design and integration challenges.

FPGAs, on the other hand, offer the fastest way to integrate a specific design into a single device.  The cost of FPGAs is traditionally higher than ASSPs or traditional ASICs, but they provide huge advantages in supporting and facilitating field upgradability, design flexibility, and faster time-to-market.  They also promise a significantly better overall total cost of ownership (TCO) compared to ASICs in many next-generation designs. 

Power-aware design

While previous generations of FPGAs at the heart of today’s IoT systems delivered the lowest static power in their class, the latest solutions deliver not only the lowest static power, but also the lowest total power. This is achieved with through comprehensive power-conscious approach spanning process technology, architecture, the design of the configurable logic, and embedded features such as SerDes, DDR2/3, and DSP blocks.

Additionally, these devices offer special power modes that reduce the power consumption to even less than the static power.  In the last two decades, many advanced CPUs and MCUs have architected various power-saving modes to address the power consumption issues caused by higher-frequencies and higher-integrations.  Only the most advanced FPGAs have been architected properly to provide similar advanced low-power capabilities while offering higher-frequency devices.   Customers now have access to low-power modes implemented in non-volatile memory-based FPGAs for the first time. 

All of these features and capabilities are particularly important in high-speed, DSP-intensive system designs.  Finite Impulse Response or FIR filters are among the DSP blocks widely used in a large number of applications to remove unwanted noise, improve signal quality, or shape signal spectrum. Several architectures of these FIR filters (Transpose, Systolic with or without symmetry) have various characteristics such as the total initial latency, the number of DSP blocks, the throughput or performance, and the number of pipeline registers.   Figure 1a & b depicts the symmetric versions of Transpose and Systolic 16-Tap FIRs and illustrates the differences between these architectures.

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Fig. 1a:  Architecture of Symmetric Transpose and Systolic 16-Tap FIRs

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Fig. 1b:  Architecture of Symmetric Transpose and Systolic 16-Tap FIRs

In a nutshell, systolic architectures use pipeline stages and reduce the inputs fanout to increase the frequency of operations. However the initial latency for N-Tap systolic FIR is (2*N -2)-cycles. The transpose architectures run at a lower frequency but have a better initial latency of (N-1)-cycles and use less sequential resources. Other criteria related to filter stability arise in particular when the number of taps is very large and weighting features need to be considered. For instance, in a voice processing application dealing with echo cancellation, the weights need to be higher at the near end, where most of the echo resides, and decrease on the later filter taps as the echo is lower.

There are dramatic differences in how much power FPGAs consume across these architectures.  Studies have been done on FPGA development kits covering 32-, 64- and 128-Tap Transpose FIR implementations using power estimation tools and – more importantly – actual silicon measurement at various temperatures.   These silicon measurements show that, when properly designed and implemented, FPGAs deliver significant power savings that are even more substantial at lower frequencies and high temperatures.

For the best-performing FPGAs, power dissipation is linear to the number of Taps.  Power dissipation figures are worse for some poor-performing FPGAs when the number of Taps is low; in others, these figures get worse when the number of Taps grows, which may highlight architectural issues.   When choosing an FPGA solution, it is important to carefully review available data for power dissipation – both static and total.

Security considerations

The IoT is essentially a collection of electronic networks that need end-to-end layered security beginning at the device level.  FPGAs can play a pivotal role in improving security through the use of unique built-in features and differentiated capabilities.  It is essential that all FPGAs used in IoT and other hyperconnected system designs be protected from cloning, reverse engineering and tampering in order to protect these embedded IPs. 

In addition, FPGAs need to become the root of trust in complex applications.  When FPGAs include embedded device security technology that works inherently, they also make base-level security easy to use and adopt.   A multi-layered approach is required, including secure hardware, design security and data security (see Figure 2).

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Fig. 2:  The best device security is achieved using a layered approach encompassing secure hardware, design security and data security.

One of the issues with SRAM-based FPGAs is the need to configure the device every time it is turned on from an external memory device. This vulnerability exposes the design to reverse engineering.  Storing the configuration information in non-volatile memory on the chip makes it impossible to capture the information and prevents reverse engineering and tampering with the design for malicious effect.

Data security is particularly important, including protecting the application data that the FPGA is processing.  Examples of data security features necessary for new applications in our hyperconnected world include:

• Hardware protection from differential power analysis (DPA) attacks. Simple and differential power analysis (SPA/DPA) can extract secret keys by measuring power consumption during cryptographic operations like bitstream loading

• The use of a Physically Unclonable Function (PUF) to generate a private public key pair is essential to authenticating machines in the IoT. Additional cryptographic functions like random number generators, hashing functions, and symmetric encryption/decryption functions are also essential and included in SmartFusion2 and IGLOO2 devices.

The IoT and other hyperconnected networks require secure and extremely power-efficient devices.  By reducing total rather than just static power and supporting a multi-layered approach to embedded security, today’s FPGA technology is helping to enable a new generation of system designs. 

Microsemi

 

 

 

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