Control method maximizes efficiency of single-phase PFC stages

The drive to improve power supply efficiency for computing and other applications no longer focuses on simply on achieving maximum efficiency at the power supply's rated output, but rather on maximizing efficiency across the full load range. This concern is reflected by energy efficiency standards such as 80Plus, which aim to raise power supply efficiency under the conditions reflecting actual product usage, and therefore establish minimum requirements for either average efficiency or the efficiency at different load levels. Since PFC (power factor correction) stages, typically boost converters, have a noticeable impact on overall power supply efficiency, there are efforts underway to optimize the efficiency of these stages across the load range. Among those working to improve PFC stage efficiency are the suppliers of PFC controller ICs. These companies are developing new control techniques to enable better PFC stage performance in line with the power supply efficiency standards. An article by Joel Turchi in the October issue of How2Power Today explains the principles of operation for a technique called CCFF (current-controlled frequency foldback). Developed by ON Semi and implemented in some of their newer PFC controller ICs, CCFF enables improvement in efficiency at both light and medium loads in single-phase PFC stages where CrM (critical conduction mode) control is typically used. Like some other methods, CCFF works to reduce switching losses by reducing the switching frequency as the load level decreases. In general, reducing the switching frequency (i.e. frequency foldback) results in very high efficiency at light load levels. However, it's more difficult to apply this technique at intermediate load levels. Mainly that's because frequency foldback also increases the conduction losses. It is then challenging to predict the optimum switching frequency that minimizes the total losses of a PFC boost converter across line and load conditions. And without being able to predict the switching losses, it is even hard to know under which operating conditions (i.e. line and load) frequency reduction should be applied. But this article shows that using the line current to control frequency reduction is an efficient approach. It is demonstrated that, rather than trying to compute switching losses directly, an easier method is to predict the trends in losses under DCM (discontinuous conduction mode) operation versus losses under CrM operation as a function of frequency reduction. From this analysis, it is seen that efficiency is optimized when the frequency is reduced in accordance with the conduction losses relative weight on the total CrM losses—in other words, as a function of the line current. This conclusion is confirmed by experimental data. As the figure below suggests, as the line current falls, so does the optimal switching frequency. The CCFF technique exploits this relationship to optimize and flatten the efficiency curve of the PFC stage over the load range. For the targeted applications, this approach is shown to be more effective than implementing frequency foldback as a function of the output power level. For more on the analysis behind this control method, experimental results, and comparisons with other PFC control techniques, see "Frequency-Foldback Technique Optimizes PFC Efficiency Over The Full Load Range," by Joel Turchi, ON Semiconductor, Toulouse, France, in the October issue of How2Power Today, which is available online at How2Power