Flexible power management for complex PCBs

• The number of power supplies on a board depends on the VLSI chip complement, the communication speed between them, and the number of other devices that require unique supplies.

This is because each of the ASICs and SoCs require multiple supplies to operate normally, including core, I/O, PLL, SERDES-channel, and memory-interface supplies. As a result, it's common for PCBs to have 15 to 25 rails. Boards with multiple power supplies typically need to implement power management functions that include power sequencing, supply-fault monitoring, trimming, and margining. Some boards may require enhanced power management functions, such as voltage scaling, non-volatile fault logging, and background sequence updating. PCB power management For example, consider a line card with four main ICs and some glue logic (Figure1). Each of the ICs requires multiple supplies and each imposes sequencing requirements. This board has 14 rails that need monitoring, sequencing, trimming, and margining. In addition, the board's design also requires logging supply faults in non-volatile memory. When a board's designers initially create the power-management algorithm, they typically only consider device-dependent sequencing. This is because the designers will not know about the power-sequencing interdependencies among different rails. In general, to finalize the power sequencing during debug, the designers should consider seven types of changes to the original algorithm:

• Adjust the time delay between turning on each of the rails or rail groups.
• Rearrange the supply turn-on sequence.
• Set the supply turn-off sequence.

Minimize conditions where the board partially powers ICs that require multiple rails during a supply fault. For example, if supply 3 fails then the power manager may need to turn off supply 4 immediately and then supplies 1 and 2. If supply 1 fails, then the appropriate sequence may be different, say, supplies 2, 3, and 4 in sequence. Generate power-good signals to various devices to get them to start operation. For example, CPUs require power-good signals not only for the core supply but also for DDR Memory, PLL, and I/O supplies. Be able to monitor digital signals to complete sequencing. For example, wait for the packet-processing ASIC's PLL-lock signal before powering up DDR supplies. Initiate power shut down on receipt of a digital control signal originating on the board or from elsewhere in the system. After all of the supplies are on, the board starts to function normally and the power management section should begin monitoring the supplies for faults. When any supply fails, then—depending on the particular supply—the power manager should interrupt or reset the CPU to prevent Flash corruption. The monitoring section of the power-management algorithm should have the following four characteristics: Identify faults of any local supply with an accuracy of 1% or better to minimize spurious supervisory fault indications and prevent missing power faults due to the supervisor's accuracy limit. This fault indication can generate an interrupt reset signal for the CPU. Sense lower supply voltages—1.5 V or below—using differential signals to minimize errors due to ground-voltage differences between the power management circuit and the local supply. Report faults within 100 ?s to minimize the duration of faulty data or instructions due to a faulty supply. Associate faults with the supervisory signals. For example, activate reset signal if supply 1, 2, 3 or 4 fails but if supply 12 fails, just interrupt the CPU to prevent faulty data transmission. The fault logging function should log the primary reason for a board shutdown. In a PCB, an initial fault usually triggers secondary actions. For example, if supply 1 fails, the board shutdown function starts to shut off the remaining supplies as per a fault-response power-down sequence. If the fault logging circuitry reacts fast enough for the supply-1 failure, the log will show supply-1 fail and the remaining supplies healthy. If the response time for fault logging is slow, it will log supplies 2, 3, and 4 faulty as well. Such a fault log is not usable. The fault logging circuit should measure supply faults accurately—within 1% error—to increase the reliability of the fault log. It should also initiate the fault logging process within 100 ?s to minimize secondary effects of the original failure corrupting the fault log.

Implementation example One common approach to implementing complex power management is to use power-good signals from DC-DC converters to monitor the supplies and use a CPLD to implement the sequencing algorithm to controlling DC-DC converter-enable signals. The CPLD also generates supervisory signals such as power-good, faulty-rail-interrupt, and reset signals (Figure 2). This implementation brings six key advantages: It meets all sequencing requirements. It's scalable with the number of supplies. There's no limitation on the power up or power down sequencing algorithm size or complexity. The sequencing algorithm can interleave supervisory signals such as power-good or faulty-voltage indications between supply sequencing. Any number of digital inputs can control the sequencing and monitoring algorithms. In-field upgrading procedures can update the sequencing algorithm without interrupting the board operation. The implementation does, however, bring four disadvantages: An cctive power-good signal does not mean that the supply is within the client IC's supply tolerance. The power-good signals from most DC-DC converters have a monitoring error of 8 to 20% but most ICs' supply tolerances are between 3 to 5%. For example, the 1.2 V core-supply rail's voltage can be 10% below the rated value—1.08 V—but the DC-DC converter power-good signal can indicate that the supply is good and the CPLD may not activate its reset signal. Consequently, the CPU may hang and overwrite a section of the Flash memory. Systems should not use the power-good signal from a DC-DC converter as a supply rail fault indication to generate supervisory signals such as reset or low-voltage interrupt. Often this type of supervisory system with enable some ICs before their supply voltages are within operating tolerances. As a result, sequencing algorithms wait for an additional time before enabling the ICs, and the board does not start-up reliably. Increases software debug time - Due to the poor accuracy of the CPU and memory supplies' power-good signals Flash corruption can occur, increasing software-degug time. It is difficult to differentiate between a software bug and unexpected program behavior due to faulty supply. Because there is no way to determine the faulty supply in hardware, software engineers waste time blaming the software bug for Flash corruption before blaming the faulty board. This can cause a delay in product release.

Implementation example One common approach to implementing complex power management is to use power-good signals from DC-DC converters to monitor the supplies and use a CPLD to implement the sequencing algorithm to controlling DC-DC converter-enable signals. The CPLD also generates supervisory signals such as power-good, faulty-rail-interrupt, and reset signals (Figure 2). This implementation brings six key advantages: It meets all sequencing requirements. It's scalable with the number of supplies. There's no limitation on the power up or power down sequencing algorithm size or complexity. The sequencing algorithm can interleave supervisory signals such as power-good or faulty-voltage indications between supply sequencing. Any number of digital inputs can control the sequencing and monitoring algorithms. In-field upgrading procedures can update the sequencing algorithm without interrupting the board operation. The implementation does, however, bring four disadvantages: An cctive power-good signal does not mean that the supply is within the client IC's supply tolerance. The power-good signals from most DC-DC converters have a monitoring error of 8 to 20% but most ICs' supply tolerances are between 3 to 5%. For example, the 1.2 V core-supply rail's voltage can be 10% below the rated value—1.08 V—but the DC-DC converter power-good signal can indicate that the supply is good and the CPLD may not activate its reset signal. Consequently, the CPU may hang and overwrite a section of the Flash memory. Systems should not use the power-good signal from a DC-DC converter as a supply rail fault indication to generate supervisory signals such as reset or low-voltage interrupt. Often this type of supervisory system with enable some ICs before their supply voltages are within operating tolerances. As a result, sequencing algorithms wait for an additional time before enabling the ICs, and the board does not start-up reliably. Increases software debug time - Due to the poor accuracy of the CPU and memory supplies' power-good signals Flash corruption can occur, increasing software-degug time. It is difficult to differentiate between a software bug and unexpected program behavior due to faulty supply. Because there is no way to determine the faulty supply in hardware, software engineers waste time blaming the software bug for Flash corruption before blaming the faulty board. This can cause a delay in product release.

Distributed sensing and centralized control An alternative is to provide accurate remote sensing and centralized control (Figure 3). This architecture is similar to the previous circuit but, due to the integration of the comparators and ADC, it requires the least number of components. For example, a Lattice Platform Manager and two Lattice Power Manager ICs implement the arrangement and provide power management for up to 36 rails. The Platform Manager integrates 12 supply voltage monitoring, a 48 macrocell CPLD and a 640 LUT FPGA. The Power Manager can sense and control up to 12 point-of-load supplies. The FPGA section of the Platform Manager implements the overall power-management algorithm and supports supply trimming and margining. This approach brings seven advantages: It provides flexible sequencing support for up to 36 rails because the FPGA implements the central power management. There is no limit to timing adjustment or sequencing response to each of the power failure conditions. The system generates supervisory signals with no compromise to reliability because the voltage monitoring accuracy is 0.7 %. In addition, because both the Platform Manager and the Power Manger support differential voltage sensing, they don't degrade measurement accuracy due to ground-voltage differences between various areas of the PCB. Because the FPGA receives all supply-fault status signals, the algorithm responds to any fault within 100 ?s and generates the supervisory signal immediately. This speed, coupled with high monitoring accuracy, minimizes the chance of Flash corruption. The system can log any supply fault into non-volatile memory in 100 ?s. This ensures that the fault log contains the primary fault. Designers can implement the power-management algorithm using HDL code or using a simplified algorithm development tool called LogiBuilder. Engineers can simulate and fine tune the algorithm, minimizing the chances of errors that require a board re-spin. In-field upgrading procedures can update the power-management algorithm without interrupting the board's operation. The device also stores a golden image, so if an event interrupts the in-system update, power cycling the board restores the previous algorithm and the upgrade procedure can begin again. The communication between the Platform Manager and the Power Manager is simple and reference designs are available. The user simply adds the reference design to the board power-management algorithm. The reference design automatically manages the communication among all devices without intervening in the main power-management algorithm. www.latticesemi.com