Reflex CES introduces first Aurora-like IP core


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Best FPGA technology enables interoperability between lead FPGA platforms

Reflex CES Aurora-like IP Core schematic

Targeting embedded, military and telecommunications/networking applications, Reflex CES, a provider of custom embedded and complex systems, announces industry's first release of Reflex CES Aurora-like IP Core, based on Altera FPGAs. The core enables interoperability between Xilinx Virtex-6 LXT, Altera Stratix IV and Stratix V GX FPGAs. The Reflex CES Aurora-like IP Core offers freedom to choose the best FPGA technology and accelerate time to market for embedded military and telecoms/networking applications. It offers a fully compliant implementation of the Xilinx Aurora 8B/10B scalable, link-layer protocol for high-speed serial communication, and allows communication between FPGAs through a backplane. "With our Reflex CES Aurora-like IP Core designers can easily migrate to new FPGA families with minimum risks, reuse their previous designs, and choose the best FPGA technology for their boards and systems using the Aurora protocol," noted Sylvain Neveu, Reflex CES co-founder and COO. Based on the Aurora 8B/10B, an open standard protocol used to transport data with higher connectivity performance for chip-to-chip and board-to-board architecture, the Reflex CES Aurora-like IP Core allows designers to move data from point-to-point across one to sixteen serial lanes at 3.125 Gbps. The core offers user flow control, native flow control, immediate and completion mode, and modules to convert interfaces to and from streaming Advanced eXtensible Interfaces (AXI). This low protocol overhead IP core offers customers minimal data rate transfer latency with minimal logic resources - less than 900 equivalent logic cells for a 1 lane configuration- for cost effective implementation. Availability The Reflex CES Aurora-like 8B/10B IP Core is available now with VHDL source code, test-benches, a reference design and user guide. Reflex CES plans to ship an Aurora-like IP Core that supports communication between FPGAs with a 64B/66B protocol at 10 Gbps. Reflex CES