RISC-V Summit, SANTA CLARA, Calif.—In a new era of computing driven by the convergence of 5G, machine learning and the internet of things (IoT), embedded developers need the richness of Linux-based operating systems. These must meet deterministic system requirements in ever lower power, thermally constrained design environments—all while addressing critical security and reliability requirements. Traditional system-on-chip (SoC) field programmable gate arrays (FPGAs) blending reconfigurable hardware with Linux-capable processing on a single chip provide developers ideal devices for customization, yet consume too much power, lack proven levels of security and reliability, or use inflexible and expensive processing architectures. In response, Microchip Technology Inc., via its Microsemi Corporation subsidiary, extended its Mi-V ecosystem by unveiling the architecture for a new class of SoC FPGAs that combine the industry’s lowest power mid-range PolarFire FPGA family with a complete microprocessor subsystem based on the open, royalty-free RISC-V instruction set architecture (ISA).
Announced at the RISC-V Summit in Santa Clara, California, Microchip’s new PolarFire SoC architecture brings real-time deterministic asymmetric multiprocessing (AMP) capability to Linux platforms in a multi-core coherent central processing unit (CPU) cluster. The PolarFire SoC architecture, developed in collaboration with SiFive, features a flexible 2 MB L2 memory subsystem that can be configured as a cache, scratchpad or a direct access memory. This allows designers to implement deterministic real-time embedded applications simultaneously with a rich operating system for a variety of thermal and space constrained applications in collaborative, networked IoT systems.
PolarFire SoC includes extensive debug capabilities including instruction trace, 50 breakpoints, passive run-time configurable Advanced eXtensible Interface (AXI) bus monitors and FPGA fabric monitors, and Microchip’s built-in two-channel logic analyzer SmartDebug. The PolarFire SoC architecture includes reliability and security features such as single error correction and double error detection (SEC-DED) on all memories, physical memory protection, a differential power analysis (DPA) safe crypto core, defense-grade secure boot and 128Kb flash boot memory.