Toshiba Announces Next-Generation Superjunction, Deep Trench Process Power MOSFETs

Date
05/17/2012

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New process to be deployed in latest 600V MOSFETs delivers ultra-low RDS(ON), reduced switching losses and lower tendency to ringing'

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Toshiba Electronics Europe has announced a new-generation of superjunction (SJ) technology for power MOSFETs. Products based on the DTMOS-IV technology will make ideal switching devices in switch mode power supplies, lighting ballasts and other power applications that demand a combination of high-speed operation, high-efficiency, and low EMI noise. Because SJ MOSFETs offer ultra-low on resistance below the silicon limit they allow device miniaturisation and PCB space saving without power loss penalties. As a result, Toshiba's new DTMOS-IV process - which is being deployed in the company's latest family of high-speed, high-efficiency 600V power MOSFETs - offers on resistance ratings that are up to 40% lower than first-generation DTMOS products for the same die size. This means that designers can now choose a 600V MOSFET in TO-220SIS package with an RDS(ON) of just 0.065?, or a similar device in a TO-3P(N) package with an RDS(ON) down to 0.04?. In addition to driving down on resistance, DTMOS-IV has also allowed Toshiba to minimise MOSFET output capacitance (Coss) for optimised SPS operation at light load. Furthermore, an optimised gate-drain capacitance (Cgd) delivers improved dv/dt switching control, while an optimised RDS(ON)*Qg figure of merit supports high-efficiency switching. Finally, by supporting lower dv/dt ratings, DTMOS-IV also reduces the tendency to ringing in high-speed switching circuitry. The DTMOS-IV technology uses a deep-trench filling process that results in a narrowing of the lateral superjunction pitch, leading to optimised overall performance. The first MOSFETs to be based on DTMOS-IV are available now in an expanded line-up that comprises DPAK, IPAK, D2PAK, I2PAK, TO-220, TO-220SIS, TO-247, TO-3P(N) and TO-3P(L) packages. www.toshiba-components.com

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