Unleashing SiC MOSFETs to Extract their Maximum Performance in Power Converter Designs

Author:
Xuning Zhang, Principal Application Engineer & Levi Gant, Application Engineer Monolith Semiconductor, Inc.

Date
05/02/2017

Categories:
MOSFETs & Power MOSFETs, Silicon Carbide (SiC)

Tag:
#Global_PSD #technology #LittelfuseESBU

 PDF
Accurate Dynamic Characterization

Dynamic characterization platform

Silicon carbide (SiC) MOSFETs switch up to five to ten times faster than silicon (Si) IGBTs and can operate at higher junction temperatures. Because they can switch on and off so quickly, they enable higher switching frequencies and therefore allow those designing inverters and other power converters to shrink the size and weight of other components, which significantly improves power density without penalizing system efficiency.

Si IGBTs typically take 50ns to 100ns to switch from the on-state to the off-state and have a current tail. Although this adds to switching losses, these silicon devices can tolerate less-than-ideal board layouts with high inductance, which makes them relatively “forgiving” in terms of converter design. In contrast, SiC MOSFETs can turn off within 10ns, which reduces power losses.

Although the fast switching of SiC devices ensures very low losses, certain design practices should be considered when designing them into a converter. Getting the maximum switching performance these devices can deliver requires a somewhat different set of design techniques than those commonly used for Si IGBTs. The side effects of fast switching, if not properly accounted for, may result in noise (EMI) injected into the gate driving circuitry, causing uncontrolled behavior, i.e. spurious turn-on. In the first installment of this series, we’ll discuss the importance of power systems designers developing a good understanding of these devices’ switching behavior, a.k.a. dynamic characteristics, when making the jump to SiC MOSFETs.

One common method for evaluating the switching characteristics of devices is through a process called a double-pulse clamped inductive load (CIL) test (Figure 1). This test involves turning on the MOSFET (Q1) twice in sequence, which is the source of the “double-pulse” part of the name. The first pulse width, in conjunction with the inductor value and bus voltage, determines the current through the device during the “turn-off” event. During the time between the first pulse and second pulse, the energy stored in the inductor circulates through the free-wheeling diode (FWD) (D2). This allows for the same set of operating parameters to be applied to the device during the rising edge of the second pulse, the “turn-on” event. The waveforms of interest in this test are Gate-Source Voltage (VGS), Drain-Source Voltage (VDS), and Drain Current (ID) (Figure2). The primary points of interest of these waveforms are the falling edge of the first pulse (turn-off) and the rising edge of the second pulse (turn-on).

Click image to enlarge

Figure 1. MOSFET switching pulse test configuration

Click image to enlarge

Figure 2. The double-pulse technique can be used to extract a variety of useful data on MOSFET switching performance.

Just as in an actual power converter, the pulse tester must be able to cope with several challenges that SiC MOSFETs’ high switching speeds present. These include voltage overshoot, conductive common-mode noise, measurement complexity, and radiated noise and near-field coupling. Addressing these challenges requires that the testing platform used provide:

  • A layout optimized to minimize inductance
  • Precise measurements of voltage and current
  • A gate drive design that isolates the control circuitry from the MOSFET to minimize noise coupling

Click image to enlarge

Figure 3.Dynamic characterization platform schematic.

The dynamic characterization platform designed by Monolith-Littelfuse incorporates several design considerations to ensure optimal collection of SiC devices’ switching behavior (Figure 3). The gate driving circuitry employs carefully selected and strategically positioned components to provide exceptionally high common-mode noise immunity.

To minimize the gate loop and ensure high fidelity switch control, optimizing the placement of components on the printed circuit board is essential. The layout must also minimize the commutation loop in the power loop portion of the circuit. Minimizing the commutation loop leads to reduced stray inductance and therefore less overshoot and ringing in the device. A return plane or trace situated directly under the gate signal trace minimizes the gate loop and helps control high frequency mirror current, thereby reducing loop inductance. Keeping the gate source and power source separated helps to reduce the Common Source Inductance (CSI).

Optimizing the layout of the power loop includes keeping the loop compact to reduce stray inductance and overlapping the DC+ and DC- on separate layers of the board to minimize loop inductance. Placing the gate loop perpendicular to the power loop also helps to reduce inductive coupling between the two circuits.

Adding copper planes can be a way to improve routing and layout in some circumstances. For example, they can reduce loop inductance and loop resistance, and reduce radiated noise from the DC bus. Copper planes are also useful for high frequency mirror current control, allowing for EMI noise reduction. However, the addition of copper planes can also increase capacitive coupling, so they should be used only where necessary.

Click image to enlarge

Figure 4.Dynamic characterization platform

To ensure the highest level of measurement precision, this dynamic characterization platform (Figure 4) features ground referenced measurement ports so that passive probes for making VGS and VDS measurements may be used; For making high bandwidth, high accuracy current measurements, a coaxial shunt is leveraged as opposed to other current measurement techniques, such as a current transformer or Rogowski coil.

With a dynamic characterization platform such as the one described in this article, a designer can extract a full suite of switching characteristics associated with a device. These characteristics include: gate charge, switching times, and switching energies. Switching test waveforms (Figure 5) allow the designer to gain a first-hand understanding of the devices and exactly how they should be implemented into their designs to achieve optimal performance.

Turn-On

 

Click image to enlarge

Figure 5a: Switching Energy

 

Turn-Off

Click image to enlarge

Figure 5b: Switching Energy

 

Click image to enlarge

Figure 5c: Switching Waveforms

 
 The waveforms in Figure 5 demonstrate that the Dynamic Characterization Platform developed by Monolith-Littelfuse exhibits exceptional design qualities that allow for accurate characterization of the device under test (DUT) with minimal concern regarding measurement error due to test platform and measurement circuit parasitics.

With an understanding of device characteristics and confidence in the testing results, a designer can now take a step forward and begin to explore:

  • Optimal driving and layout techniques
  • SiC MOSFET protection
  • EMI noise propagation control
  • Impact of packaging on device performance

Each of these topics will be featured in subsequent installments of the “Unleashing SiC MOSFETs to Extract Their Maximum Performance in Power Converter Designs” series.

Littelfuse

Monolith Semiconductor

Related articles

 Long-Life Ceramic/Quartz-Based UVC Emitting Diode
 Coupled Exploration of Light and Matter
 Ambient Light Sensor Targets Wearables and Smartphones