Working with High Voltage Renewable Energy Sources

Jonathan Dodge, Senior Applications Engineer, UnitedSiC


How a switch from 3L-NPC to 3L-ANPC architecture can improve inverter efficiency

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Table 1: Switch states for a 3L-NPC phase leg

The energy landscape is shifting, with growing concern over the use of carbon-based fuels and greater momentum behind making the most of renewables.  Photovoltaic (PV) panels and wind turbines are a common site across the landscape and along coastlines.  Large renewable installations require higher operating voltage to reduce installation cost and power loss.  This creates a challenge for power inverter designs that take the higher DC input voltage and convert it to AC output for distribution on the grid.

The two-level voltage source inverter (2L-VSI) is a popular topology in low voltage applications, but in higher voltage applications, it is widely displaced by more complex but more efficient multi-level topologies, such as the three-level neutral point clamped (3L-NPC) inverter. Adding a third, or neutral, state reduces switching loss and the strain on the filter and switching components, which makes it better suited to higher operating voltage compared to the 2L-VSI. A further development is the 3L-ANPC, or active neutral point clamped topology, which replaces the clamp diodes with transistors (Figure 1a and 1b). The resulting circuit is more complex, with six transistors per leg. Understandably, engineers may be unsure of which topology to choose for their application, particularly considering cost since the transistors and associated gate drives are more expensive than the diodes they displace.

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Figure 1: Phase leg based on the 3L-NPC and 3L-ANPC topologies

This article provides some guidance to answer the question of what is gained from the added cost and complexity of the ANPC topology versus 3L-NPC. The added controllable switches open the possibility of forcing switching loss to specific transistors, and of significantly increasing the overall efficiency. An overview of three ANPC modulation strategies is presented and compared with 3L-NPC. Control complexity is an important design consideration, so some insights on implementation are provided.

Comparing inverter modulation schemes

With the addition of two more transistors, the total number of possible switch states increases from 16 (3L-NPC) to 64 (3L-ANPC). However, while both inverters have states categorized as safe, hazardous, and destructive, the addition of Q5 and Q6 renders some of the hazardous states in 3L-NPC as safe in 3L-ANPC when either or both of these transistors are conducting, as they act as voltage clamps.

To simplify the description of the operation, transistors are grouped into commutation cells. Referring to one leg of a 3L-NPC inverter shown in Figure 1a, Q1 and Q3 are in one cell, and Q2 and Q4 in another (Table 1).

During the O state, the output (AC terminal in Figure 1) of a phase leg is clamped to the neutral point (center of the DC link capacitors) by Q2 and Q3 being held on, and either D5 or D6 conducting, depending on current direction. The AC terminal is tied to the positive or negative rail during the P or N states respectively.

In general, the 3L-NPC inverter is controlled by two PWM signals, easily generated by a microcontroller PWM peripheral, with signal inversion and deadtime interlock added either by the microcontroller or by a gate driver.

For the 3L-ANPC modulation strategy referred to here as PWM1, the number of cells increases to three, and there are two neutral states (Table 2).

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Table 2: Switch state for a 3L-ANPC phase leg using PWM1 strategy

PWM1 is similar to 3L-NPC modulation with synchronous rectification of Q5 and Q6, which improves efficiency. It differs in that the current is forced through Q2 and Q5 in the O+ state during the positive half of the AC line cycle, and through Q3 and Q6 in the O- state during negative half cycle, regardless of current direction (regardless of power factor). Because Cell 2 always switches at line frequency, switching loss concentrates in Cells 1 and 3, specifically in Q1 and Q4 during inverter mode (DC to AC operation), and Q5 and Q6 in rectifier mode (power flows from AC to DC).  Three PWM channels in a microcontroller are required per inverter leg, plus signal inversion and deadtime interlock.

The ANPC PWM2 strategy has the same three commutation cells as PWM1, but with different switch states. Switching loss focuses on Cell 2 only for both inverter and rectifier mode (and anything between).

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Table 3: Switch states for a 3L-ANPC phase leg using PWM2 strategy

A main advantage of PWM2 is the possibility of using lower performance, lower cost devices for each switch position except Q2 and Q3, which would benefit from the performance advantages of silicon-carbide.  This advantage fades in light of the next ANPC PWM strategy, called here PWM4 (skipping one called PWM3 for the sake of brevity).

With PWM4, there are two commutation cells and one neutral state, similar to 3L-NPC (Table 4).

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Table 4: Switch states for a 3L-ANPC phase leg using PWM4 strategy

Cell 1 and Cell 2 alternate between line and switching frequency during the negative and positive AC half-cycles, respectively. Current flows in either direction through both clamp paths, reducing conduction losses in Q2, Q3, Q5, and Q6. However, by using devices that have equal forward and reverse conduction losses, such as UnitedSiC cascode FETs, the losses in each FET during the neural state is reduced by half. Another advantage of using these devices is that they exhibit no reverse or forward knee voltage, resulting in higher efficiency. Figure 2 shows the state diagram for this PWM strategy.

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Figure 2: The PWM4 strategy state diagram for a 3L-ANPC phase leg

As with 3L-NPC, PWM4 is easily implemented with two microcontroller PWM channels. Transitions between states is seamless, with only two deadtime interlock states added as required to avoid hazardous states during switching. This facilitates neutral point balancing schemes such as redundant short vectors and nearest three virtual space vectors.

Choosing the right PWM strategy

A power loss estimate based on operating conditions is essential for selecting the most appropriate topology, PWM strategy, and power semiconductors. By making some assumptions about the heatsink temperature, along with knowing some critical information about the diodes and FETs used (such as switching loss versus current, and the change in RDS(ON) versus junction temperature, and temperature increase with power loss), this can be modelled. Various configurations can be quickly analysed to determine which merit further investigation, and which should be dropped.

Consider for example a 150 kVA three-phase inverter switching at 25 kHz, with DC input of 1160 V, and an AC line-to-line voltage of 600 V rms. Figure 3 shows a power loss comparison for 3L-NPC and 3L-ANPC topologies using all three of the PWM strategies outlined earlier. In this example, the FETs are UnitedSiC UF3SC120009K4S, a 1200 V, 9 mΩ SiC cascode FET. The results clearly show that PWM4 offers the greatest advantage in total losses, but especially for conduction loss in inverter mode (Figure 3a).  PWM1 and PWM2 are close behind in rectifier mode.  Here again though, the efficiency improvement of PWM4 versus 3L-NPC support the argument that the added cost and complexity of ANPC is justifiable.

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Figure 3: Power loss estimates for 3L-NPC and 3L-ANPC inverters with two parallel UF3SC120009K4S in each switch position, except 3L-NPC which has two parallel UJ3D1250K2 SiC diodes for D5 and D6; (a) inverter mode with power factor = 1, and (b) rectifier mode with power factor = -1

A further advantage of implementing PWM4 is that the PWM generation is identical to that of 3L-NPC, with Q5 and Q6 gate signals copied from Q3 and Q2 respectively. This means upgrading a design from a 3L-NPC topology to 3L-ANPC is simpler when adopting this switching strategy than one of the others discussed earlier.

Optimizing the inverter

Since some switch positions are more lightly loaded than others, it makes sense to save cost by using smaller FETs, or even low cost IGBTs in some switch positions. A further consideration, particularly for solar inverters, is how the circuit performs with high ambient temperature, and the heatsink reaches 100 °C, for example. Focusing on the ANPC topology with PWM4 modulation, a comparison is made with two parallel UF3SC120009K4S installed in Q1 and Q4, as before.  Q2 and Q3 are populated either with two parallel UF3SC120016K4S, a 1200 V, 16 mΩ SiC cascode FET, or two parallel high speed 1200 V, 75 A IGBTs, each with co-packaged diode.  Similarly, Q5 and Q6 contain two parallel UF3C120040K4S, a 1200 V, 35 mΩ SiC cascode FET, or two parallel of the same 1200 V, 75 A IGBT as before. The loss calculation results indicate a clear difference in efficiency, as shown in Figure 4, especially in rectifier mode (Figure 4b). With inverter mode (Figure 4a), IGBTs in Q5 and Q6 show about the same performance as with SiC FETs, while an increase in power loss in Q2 and Q3 impels further scrutiny of choosing IGBTs for these switch positions.

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Figure 4: PWM4 combined semiconductor efficiency with Tsink = 100 °C, two parallel UF3SC120009K4S per Q1 and Q4 switch positions; two parallel UF3SC120016K4S or two parallel 1200 V, 75 A high speed IGBT per Q2 and Q3; and two parallel UF3C120040K4S or two parallel of the 1200 V, 75 A IGBTs per Q5 and Q6; (a) with PF = 1, and (b) PF = -1

The difference in performance is due to the lower switching losses of the SiC FETs, as expected, but interestingly, conduction loss is also lower. Part of this can be attributed to the elimination of the knee voltage that is present in IGBTs, but also to the exceptionally low RDS(on) of the UnitedSiC cascode FETs. This is a crucial design feature and one that needs to be considered when selecting the inverter topology and PWM strategy based on operating conditions.


By assessing the power losses and overall efficiencies available from different power components, engineers are better equipped to make the right decision when selecting topologies, switching strategies, and power semiconductors for high power, high voltage applications. Moving from a 3L-NPC to 3L-ANPC architecture introduces a cost increase because diodes are replaced with more expensive transistors plus gate drives. However, as shown here, the benefits can outweigh the additional cost and design complexity in applications that demand high efficiency. The modulation strategy described here as PWM4 for ANPC inverters results in substantially lower total power loss and yet is very similar in terms of control to 3L-NPC.