Altera is demonstrating its portfolio of FPGA and power solutions at the Applied Power Electronics Conference, (APEC) being held at the Charlotte Convention Center, in Charlotte, North Carolina, from March 15 to 19. System designers can use field-programmable gate arrays (FPGAs) and SoCs coupled with Altera Enpirion power solutions to achieve new levels of power performance and efficiency while saving board space in their designs. In particular, the powering of industrial applications will be featured, with a focus on managing voltage modulation and quad axis power for motor control. Learn more about Altera Enpirion power solutions at www.altera.com/enpirion and Altera industrial solutions at www.altera.com/industrial.
Demonstrations in the Altera booth #123 include the following solutions:
Four phase, 120A, Digital PowerSoC Solution – Demonstration of a new integrated digital DC-DC converter optimized for high-end FPGAs offering the highest efficiency in the smallest footprint. Meets the toughest specification requirements for high end generation 10 FPGA core power supply rails and features Adaptive Digital Control and PMBus Communications.
FPGA Based Envelope Tracking Voltage Modulator (ETVM) – An extremely high bandwidth power supply optimized for powering telecommunication RF amplifiers and other high performance loads. ETVM technology can be used for powering any application requiring the following: Arbitrary voltage modulation, high efficiency, density or bandwidth; and a high slew rate or low and consistent latency. It can be adapted to various topologies when high density and high bandwidth are required.
400V Quad-axis power control using an FPGA: Demonstration features a board that supports up to four permanent magnet synchronous (PMSM) motors or brushless DC (BLDC) motors and illustrates power factor correction. It also shows DC Voltage measurement and Sigma-delta current conversion controlled by the FPGA delivering four simultaneous Field Oriented Control (FOC) loops in 62.5 µs with PWM, ADC interface, encoder interface and a network interface all integrated as a single-chip implementation.
