Avnet Electronics will host a series of SpeedWay Design Workshops™, featuring Microsemi’s low-power, cost-optimized IGLOO®2 FPGAs. The workshops, taught by Avnet technical experts, kick off Feb. 25 in San Jose, Calif., and will be held in 26 cities throughout North America.
As one of the largest distributors of electronic components in the world, Avnet understands the value Microsemi’s IGLOO2 family provides to a comprehensive range of mainstream market applications. The Microsemi IGLOO2 delivers low-power consumption and innovative security features that contribute to significant competitive end-application differentiation for Avnet customers. SpeedWay Design Workshops enable Avnet’s customers to immediately start using Microsemi FPGAs in their designs.
The training is recommended for FPGA designers, system architects and design engineers who are new to IGLOO2 FPGAs or seek to enhance their expertise with low power and secure designs. Workshop topics range from introductory to advanced, demonstrating the techniques and tools used to create a basic IGLOO2 FPGA design that utilizes IGLOO2 FPGA fabric, built-in PCI Express® controllers, low power design capabilities, advanced security processing and other important features used in FPGA-based designs.
“IGLOO2 FPGAs provide up to three times lower static power than competing solutions, making them a great option for designs that need significant overall system power reduction,” said Rondekka Moore, vice president, demand creation, Avnet Electronics Marketing Americas. “Through these SpeedWay courses, Avnet provides engineers a demonstration of how to analyze power for their own designs — whether they just started learning about FPGAs or they’re designing complex systems for industrial, military, aviation, communications or medical applications.”
“Due to its size and global footprint, Avnet is the ideal partner to facilitate these hands-on workshops on behalf of Microsemi,” said Jorgen Makitalo, global distribution channel director at Microsemi. “Avnet has the experience and technical know-how to train design teams who are ready to implement Microsemi’s next-generation, low-power, mainstream IGLOO2 FPGAs.”
During the SpeedWay events, attendees will learn about the capabilities, features and usage of IGLOO2 FPGAs.
-Learning how flash based FPGAs can deliver capabilities including DSPs, SERDES, high speed I/Os and integrated memory blocks
-Introduction to the high performance memory subsystem (HPMS)
-Design and data security features of IGLOO2 FPGAs
-Overview of the 5Gbps SERDES, PCIe, XAUI / XGXS+ Native SERDES capabilities
-Debug capabilities of the device and software tools
-The hands-on labs will utilize the IGLOO2 Evaluation Kit, which supports:
-Introduction to the FPGA design flow including timing and power analysis
-System builder session for configuring the high performance memory subsystem
IGLOO2 FPGA Low Cost Evaluation Kit capabilities:
-IGLOO2 FPGA in the FGG484 package (M2GL010T-FGG484)
-64 Mb SPI Flash memory
-512 MB LPDDR
-PCI Express Gen2 x1 interface
-Four SMA connector for testing of full-duplex SERDES channel
-RJ45 interface for 10/100/1000 Ethernet
-JTAG/SPI programming interface
-Headers for I2C, SPI, GPIOs
-Push-button switches and LEDs for demo purposes
-Current measurement test points
The full-day trainings cost $99. Attendees will receive an IGLOO2 FPGA Evaluation Kit.