SiTime Enables 5G Vision of 0 Downtime w/ 10x Reliability


MEMS Clock-System-on-a-Chip Reshapes $1 Billion Silicon Clocks Market

SiTime Corporation announced the Cascade family of MEMS clock ICs for 5G, wireline telecom and datacenter infrastructure. This clock-system-on-a-chip (ClkSoC) family, the SiT9514x, consists of clock generators, jitter cleaners,and network synchronizersthat deliver multiple clock signals in a system. This clock family uses SiTime’s recently launched third-generation MEMS resonators that deliver higher performance with lower power.

Communications and enterprise electronics have previously used clock ICs with external quartz references to integrate multiple timing functions and to distribute clock signals. SiTime’s new, all-silicon clock architecture provides more integration by integrating a MEMS resonator reference inside the package. More importantly, with SiTime’s proven MEMS technology, the Cascade clock-system-on-a-chip delivers up to 10 times higher reliability and resilience, enabling the 5G vision of zero downtime. Either standalone or together with SiTime’s MEMS TCXOs and OCXOs, the SiT9514x delivers a complete timing solution for applications such as 5G RRUs, small cells, edge computers, switches, and routers.

5G is expected to deliver 10 times faster speeds and 10,000 times more data, with 50 times lower latency and zero downtime. To make this vision a reality, 10 to 30 times more devices will be deployed, many of them in uncontrolled environments close to the consumer. Each of these connectivity gains is dependent on the accuracy, resilience and reliability of the timing heartbeat of the system. Silicon MEMS timing technology inherently provides better reliability and resilience which is critical to support the quality of service planned for 5G.

Benefits of SiTime’s Complete Clock-System-on-a-Chip

  •     Integrated MEMS resonator eliminates issues with quartz such as capacitive mismatch, activity dips, susceptibility to shock, vibration, and EMI
  •     Four independent PLLs, with maximum flexibility to support time synchronization applications where multiple independent clock domains are required
  •     Up to 11 outputs with an operating frequency range of 8 kHz to 2.1 GHz, as well as a 1 PPS (pulse per second) output, for maximum frequency agility
  •     Programmable PLL loop bandwidth down to 1 milli-Hz for maximum filtering of wander or network noise in IEEE 1588 and synchronous Ethernet
  •     Fail-safe operation in case of input clock failures through faster hitless switching between four independent inputs. In such a situation, the device automatically switches to different input clock sources with minimum phase transient at the output, allowing the downstream PLL to remain locked, and the system to continue to operate reliably
  •     Excellent PSNR for highest performance in the presence of power supply noise
  •     Minimal external filtering circuits for simpler design, space savings, and BOM reduction
  •     Rich programmable features and configuration options: (1) Blank ISP (in-system programmable) devices provide maximum flexibility; (2) Pre-programmed devices enable system boot up without software configuration for maximum simplicity
  •     EVBs and TimeMaster software enable users to map clock configurations and generate the scripts for software integration, which speeds development


The SiT9514x clock-system-on-a-chip family is sampling now. For more information, visit SiTime Corporation.