Technical Features

December 2012

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Figure 1: MOSFET channel punch-through showing outputs from previous SPICE simulators vs. QSPICE

QSPICE: A Mission to Get SPICE Right

Siddharth Mohan, design engineer, Qorvo

Qorvo’s QSPICE™ simulator for analog and mixed-signal simulation provides power designers with the tools to confidently evaluate their designs. Free to use, QSPICE improves SPICE basics, supports large amounts of digital logic without performance penalties, and delivers the speed and accuracy needed for rel

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Date:

11/29/2024

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Figure 1: Inductor-current waveform

Power inductors and peak-current handling capability

Nelson Garcia, Engineering Manager, Renco Electronics

As high-tech electronic products and their power supplies continue to shrink in size, design engineers should look closely at the peak-current handling capability of power inductors. Design engineers

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Date:

12/23/2012

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Figure 1: SOA (a) and ZthJC (b) charts for the BSC014N04LS

Thermal design considerations for thin power MOSFETs

Ralf Walter, Application Engineer, Infineon Technologies AG

Thermal challenges accompany almost all advances in power-electronic designs. Load cases not covered under a datasheet's parameters are often particularly problematic. Each new MOSFET generation

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Date:

12/19/2012

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String central inverter system

Frank Hinrichsen and Mark Ahmling, Wind and Sun Technologies

Planners of photovoltaic power plants are no longer bound to string inverter concepts if multiple MMP(maximum power point)-trackers are required. Central inverter systems are, today, standard for

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Date:

12/18/2012

Control and protection rests on measurement precision

Stéphane Rollier, Product and MarCom Manager, and Bernard Richard, Business Development Manager, LEM

Designers of solar power—photo-voltaic or PV—generating systems face some of the same problems as their counterparts in any other power-related technology: the need to constantly improve performance, reliability, longevity, and—above all—efficiency. As with any engineering endeavour, improved performance re

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Date:

12/12/2012

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Figure 1: The DiSEqC application circuit

Designing a DiSEqC-antenna phantom power-supply

Andrea Longobardi, Product Definer and Corporate Applications Engineer, Maxim Integrated

The DiSEqC (digital satellite equipment control) standard is a communication protocol developed by Eutelsat used between a satellite receiver (decoder), defined as the master, and satellite peripheral

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Date:

12/04/2012