Technical Features
December 2012
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Figure 1: Two-stage 48 V power architecture for an AI server, showing IBC and downstream point-of-load regulation
1. AI server power delivery raises the density challenge
AI accelerators concentrate more computing, and therefore more electrical power, within limited rack and board space. Supplying these loads is not simply a matter of increasing converter output. Every power‑delivery stage must balance conversion ef
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Date:
08/31/2026
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Figure 1: Inductor-current waveform
As high-tech electronic products and their power supplies continue to shrink in size, design engineers should look closely at the peak-current handling capability of power inductors.
Design engineers
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Date:
12/23/2012
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Figure 1: SOA (a) and ZthJC (b) charts for the BSC014N04LS
Thermal challenges accompany almost all advances in power-electronic designs. Load cases not covered under a datasheet's parameters are often particularly problematic.
Each new MOSFET generation
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Date:
12/19/2012
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Planners of photovoltaic power plants are no longer bound to string inverter concepts if multiple MMP(maximum power point)-trackers are required. Central inverter systems are, today, standard for
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Date:
12/18/2012
Designers of solar power—photo-voltaic or PV—generating systems face some of the same problems as their counterparts in any other power-related technology: the need to constantly improve performance, reliability, longevity, and—above all—efficiency. As with any engineering endeavour, improved performance re
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Date:
12/12/2012
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Figure 1: The DiSEqC application circuit
The DiSEqC (digital satellite equipment control) standard is a communication protocol developed by Eutelsat used between a satellite receiver (decoder), defined as the master, and satellite peripheral
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Date:
12/04/2012
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