Technical Features

July 2013
Optimizing Flying Capacitor Multilevel Converters for GaN Technology

Figure 1: Power schematic circuit for the bi-directional three-level, two-phase converter

Introduction Modern power systems demand higher efficiency, increased power density, and reduced electromagnetic interference (EMI)—all while adhering to shrinking size constraints. Among the converter topologies addressing these challenges, the Flying Capacitor Multilevel (FCML) converter stands out for it
Date:
05/30/2025
MEMS Time-Keeper Extends Standby Life of Mobile Devices

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Figure 1: Block diagram showing high-level architecture of a smart phone

With un-tethered instant access to data, news and entertainment, consumers are spending more time on Smartphones and mobile devices. Device users are demanding faster connectivity, multi-core Ghz+
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Date:
07/08/2013

Filter capacitor considerations

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Figure 1. Theoretical (left) and Actual (right) models of a capacitor.

Due to the constant evolution of consumer electronics, efficient power conversion is critical for reliable performance, and the filtering of output ripple is a critical factor in supplying consistent
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Date:
07/08/2013
Technology trends in mobile charging

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Figure 1: Greenchip solution based on TEA1720B and TEA1705

Mobile battery capacity is increasing to cope with the extra energy demands of power-hungry features, larger displays and more powerful CPUs. With bigger batteries to charge, how can system designers
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Date:
07/08/2013
New power architecture addresses PFC load efficiency issues

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Figure 1: Block Diagram of an Isolated AC/DC Compound Converter

As Power Factor Correction (PFC) migrates to lower power AC/DC converters, maintaining efficiency at low loads becomes an increasing challenge. The approach usually taken involves adding an extra
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Date:
07/08/2013
Next-generation SJ MOSFETs extend performance of silicon-based power devices

Figure 1

For more than a decade, development of Infineon's CoolMOS™ super-junction (SJ) MOSFET technology has extended the "silicon limit line" that restricts the performance of planar-type power MOSFETs.
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Date:
07/05/2013
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